We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Visitor lucaj88
Registered: ‎05-25-2019

How to sum two ap_axiu stream AXI4_STREAM interface

I'm new with HLS and in general with Digital Design. I've got an Electronic Engineering background but I have never gone in depth with digital electronic system.

I'm trying to implement a simple summation of two stream vector (int type) using AXI interface. Starting from a simple sum of vector by an integer I try to modify the source code for HLS:


#include <hls_stream.h>
#include <ap_axi_sdata.h>

typedef ap_axiu<32,1,1,1> stream_type;
typedef qdma_axis<32,0,0,0> stream_res_type;

void add_vectors(stream_type* in_data1, stream_type* in_data2, stream_res_type* out_data) {
#pragma HLS INTERFACE ap_ctrl_none port=return
#pragma HLS INTERFACE axis port=in_data1
#pragma HLS INTERFACE axis port=in_data2
#pragma HLS INTERFACE axis port=out_data

    out_data->data = in_data1->data + in_data2->data;
    out_data->keep = in_data1->keep || in_data2->keep;
    out_data->last = in_data1->last;

It's hard to me to figure out the side signals for out_data.

For the handshaking process I clearly want that TLAST signal rises when both in_Data1->TLAST and in_Data2->TLAST rise. I couldn't set in this way since error from compiler so for testing I just put it equal to the first signal.

For TKEEP signal, I don't really know how to set it, so I just set high when both the signals go high.

Please, keep in mind that I choose AXI stream because it seems very flexible and not constrained to the data dimensions. Also I think that DMA might be a fast solution for data transfer.

Furthermore, how can two stream signals be managed with an AXI DMA? I have always seen (in simple examples) AXI DMA with just one M_AXIS_MM2S but for this case I think I need two MM2S port. Is this possible?

Sorry for the confused questions but It is all almost new to me. 

Thank you

0 Kudos
3 Replies
Scholar u4223374
Registered: ‎04-26-2015

Re: How to sum two ap_axiu stream AXI4_STREAM interface

@lucaj88 First things first, I would recommend using the hls::Stream class for this. I find that it helps to reduce human error (because it simply won't let you do things like random access, whereas a pointer will allow that). I can provide a simple example if you want it.


TLAST is a tricky one. Using your original idea (TLAST when both streams have TLAST), what happens if one of the streams loses sync with the other? Now the TLASTs never line up with each other... Even if it's logically impossible for them to ever be out of sync, I'd still try to design the system "just in case" it does happen. In my code, I prefer to set it up so that when one stream finds TLAST, that stream stops - and the other one keeps getting read until it also finds TLAST. That way they automatically re-synchronize.

TKEEP only matters if you use it. I always just leave it set to 0xFF (all ones).


In this application, if the intention is to add two sets of data from RAM and put them back into RAM, I suspect that an AXI Master will do the job more easily for you. Streams are great when you want to chain a bunch of blocks together in a long line, without putting data back in RAM in the middle. If each block reads from RAM and writes to RAM, an AXI Master on each block will simplify your design substantially.

Visitor lucaj88
Registered: ‎05-25-2019

Re: How to sum two ap_axiu stream AXI4_STREAM interface

Thanks for the advice.
What the difference between having an AXI Master and two AXI DMA + Axi Interconnect?
0 Kudos
Scholar u4223374
Registered: ‎04-26-2015

Re: How to sum two ap_axiu stream AXI4_STREAM interface

The big difference is that the DMA will have a bunch of AXI Masters all arguing over who gets access to the bus (through an AXI Interconnect or Smartconnect). You can get some interesting deadlock situations there...


Whereas a single AXI Master on the block means that you save some hardware and eliminate the deadlocks. Because it can perform random reads, you can do things like pull 64 values from one location into a buffer, pull 64 values from another location into a buffer, and then add those and send them out to another location - all with one piece of hardware.