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Observer xyzhou
Observer
300 Views
Registered: ‎09-24-2018

How to use BRAM to read/write 8-bit array in Vivado block diagram?

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Hi, everyone. I am quite new to HLS and Vivado.

I am working on making a function using HLS and then export the bitstream for my Pynq-Z1 board.

 

So my function has four input variables:

input1 is an array of ap_fixed<8,2>

layer10_out is an array of ap_fixed<8,2>

const_size_in_1, const_size_out_1   are two unsigned short number for settings.

 

void fecpred0(
input_t input1[N_INPUT_1_1*N_INPUT_2_1],
result_t layer10_out[N_LAYER_9],
unsigned short &const_size_in_1,
unsigned short &const_size_out_1
) {

// self-defined interface
//#pragma HLS INTERFACE ap_ctrl_none port=return
#pragma HLS INTERFACE s_axilite port=return bundle=CRTL_BUS
#pragma HLS INTERFACE s_axilite port=const_size_in_1 bundle=CRTL_BUS
#pragma HLS INTERFACE s_axilite port=const_size_out_1 bundle=CRTL_BUS
#pragma HLS INTERFACE bram port=input1
#pragma HLS INTERFACE bram port=layer10_out

..............

}

 

I am currenly using interface like above, after the synthesis in Vivado_HLS, I am confused how to create a block diagram for this.

Any suggestions? Thank you!

 

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1 Solution

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Moderator
Moderator
252 Views
Registered: ‎05-31-2017

Re: How to use BRAM to read/write 8-bit array in Vivado block diagram?

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Hi @xyzhou ,

Please check chapter9 of UG 871 on how to use the HLS generated IP in Vivado IP Integrator.

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2 Replies
Moderator
Moderator
253 Views
Registered: ‎05-31-2017

Re: How to use BRAM to read/write 8-bit array in Vivado block diagram?

Jump to solution

Hi @xyzhou ,

Please check chapter9 of UG 871 on how to use the HLS generated IP in Vivado IP Integrator.

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Observer xyzhou
Observer
206 Views
Registered: ‎09-24-2018

Re: How to use BRAM to read/write 8-bit array in Vivado block diagram?

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thanks
I will take a more careful look at it
currently I actually use the axi-lite for data transfer, will change to axis for a trial
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