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cerilet
Explorer
Explorer
4,918 Views
Registered: ‎08-26-2014

Is it possible to have an IP running at 5MHz and the AXI at 250MHz?

Hello,

 

I am developing an IP which the best implementation I have is using a 5MHz clock (200ns), where it is able to perform all the operations with 0 latency (full-combinatorial). It needs 5 input variables and outputs 5 more, all of them 32-bit wide.

 

I want to control it using the PS but obviously, if I use an AXI Master with the clock running at 5MHz, the time it needs to transfer all the data is quite large (40 cycles of 200ns).

 

I was wondering if there is the possibility to have the AXI Master running at 250MHz and the IP at 5MHz.

 

Thanks.

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muzaffer
Teacher
Teacher
4,912 Views
Registered: ‎03-31-2012

@cerilet you can make the axi-slave run at 250 MHz, collect all 5 words in registers, start the ip, wait till done (ie count to 50) and then write the resulting 5 words back to memory.

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Anonymous
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@muzaffer I think @cerilet is asking is it is possible to have separate clocks for the AXI light and the internal logic.
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muzaffer
Teacher
Teacher
4,848 Views
Registered: ‎03-31-2012

@Anonymous it wasn't entirely clear to me whether @cerilet had an axi-lite interface or an m_axi. Based on master in this post, I assumed he had an m_axi.

 

In either case, it is certainly possible to have the axi protocol management and the IP run at different clocks. The easy solution is an axi interconnect which has the clock-domain crossing feature in it. The harder feature is to code some RTL running on faster side controlling/checking start/done signals to remove some unnecessary cycles. But my suggestion requires separating axi protocol management and the internals of the IP into separate blocks. I am not sure how HLS would handle such a case.

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u4223374
Advisor
Advisor
4,824 Views
Registered: ‎04-26-2015

The easiest approach for HLS is to pack the input/output data into a very wide bus (5*32-bit = 160-bit; although you might need to go to 256-bit. I've had issues with non-power-of-2 widths before). Then stick an AXI Interconnect between the HLS IP core and the RAM to do the conversion from a wide, slow bus to a thin, fast bus.

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