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Contributor
Contributor
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Registered: ‎07-17-2019

LUT as Distributed RAM over-utilized in Top Level Design

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I got an error message while I am building the kernels and host program. 

Hardware: zcu102.

Software: Vitis Core Development Kit (2019.2)

Any idea about error? Is this because that the FPGA on zcu102 don't have enough LUT for my project? What should I do to use less LUT in my program?

Or I should "Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.". Where to set this tcl parameter? Thanks!

 

Following are the error message:

===>The following messages were generated while processing /harddisk1/xxxx/Projects/Vitis_test/wsp_phenix_track/noise_removal/build_dir.hw.zcu102_base/link/vivado/vpl/prj/prj.runs/impl_1 :
ERROR: [VPL UTLZ-1] Resource utilization: LUT as Distributed RAM over-utilized in Top Level Design (This design requires more LUT as Distributed RAM cells than are available in the target device. This design requires 147168 of such cell types but only 144000 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.)
ERROR: [VPL UTLZ-1] Resource utilization: LUT as Memory over-utilized in Top Level Design (This design requires more LUT as Memory cells than are available in the target device. This design requires 150350 of such cell types but only 144000 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.)
ERROR: [VPL UTLZ-1] Resource utilization: RAMB18 and RAMB36/FIFO over-utilized in Top Level Design (This design requires more RAMB18 and RAMB36/FIFO cells than are available in the target device. This design requires 5657 of such cell types but only 1824 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)
ERROR: [VPL UTLZ-1] Resource utilization: RAMB36/FIFO over-utilized in Top Level Design (This design requires more RAMB36/FIFO cells than are available in the target device. This design requires 2817 of such cell types but only 912 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)
ERROR: [VPL UTLZ-1] Resource utilization: RAMB36E2 over-utilized in Top Level Design (This design requires more RAMB36E2 cells than are available in the target device. This design requires 2817 of such cell types but only 912 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)
ERROR: [VPL 4-23] Error(s) found during DRC. Placer not run.
WARNING: [VPL 60-732] Link warning: No monitor points found for BD automation.
ERROR: [VPL 60-704] Integration error, problem implementing dynamic region, place_design ERROR, please look at the run log file '/harddisk1/xxxx/Projects/Vitis_test/wsp_phenix_track/noise_removal/build_dir.hw.zcu102_base/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information
ERROR: [VPL 60-1328] Vpl run 'vpl' failed
ERROR: [VPL 60-806] Failed to finish platform linker
INFO: [v++ 60-1442] [11:20:57] Run run_link: Step vpl: Failed
Time (s): cpu = 00:00:17 ; elapsed = 00:30:43 . Memory (MB): peak = 576.969 ; gain = 0.000 ; free physical = 44435 ; free virtual = 117240
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
Makefile:142: recipe for target 'build_dir.hw.zcu102_base/tracking.xclbin' failed
make: *** [build_dir.hw.zcu102_base/tracking.xclbin] Error 1
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Highlighted
467 Views
Registered: ‎06-21-2017

You are also over utilizing the block RAM in your design.  FPGAs do not have a lot of internal memory.  These are best used for small buffers.  If you need a large memory, you should find a way to utilize the DDR RAM attached to the FPGA.  The ZCU-102 has external memory attached to both the PL and PS side of the chip.  The other alternative is to change your design to use less memory.

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468 Views
Registered: ‎06-21-2017

You are also over utilizing the block RAM in your design.  FPGAs do not have a lot of internal memory.  These are best used for small buffers.  If you need a large memory, you should find a way to utilize the DDR RAM attached to the FPGA.  The ZCU-102 has external memory attached to both the PL and PS side of the chip.  The other alternative is to change your design to use less memory.

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Advisor
Advisor
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Registered: ‎04-26-2015

Adding to what @bruce_karaffa has said, you're not just using a bit more - you're using far more RAM than the chip has available. This will likely require a major redesign of your system to move some less-used data to off-chip RAM.

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Contributor
Contributor
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Registered: ‎07-17-2019

Hi, @bruce_karaffa @u4223374  I really appreciate the answers from you guys.

According to the error message, 912 unites of 36K block RAM yields to 32.1 Mb, which matches the spec sheet of device UltraScale+ XCZU9EG-2FFVB1156.

I have done some testing on this projects by change the input data's size. I've 3 kernel in this project, and each kernel has multiple inputs. I noticed while I changes the inputs' data size, the Block RAM usage varies too. If I reduce the kernel inputs' data size to certain point, the project can be built without the over-utilized LUT and BRAM errors. 

But one thing I don't quite understand is that according to my project requirement, the data input size to all 3 kernel is roughly about 650K Byte, which is far less then the Block RAM on the device, 32.1 Mb. Why I am still getting the over-utilized BRAM error? Thank you!

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Contributor
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Registered: ‎03-01-2020

@lzhao Block RAM usage is not just about size, it is also about number of ports. Each Block RAM only has two ports and depending on the number of accesses to your buffers (due to buffer partitioning), your design might require many more blocks that would be required just to support the size of your buffer.