cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
j_ney
Contributor
Contributor
738 Views
Registered: ‎11-26-2017

Latency Difference Synthesis, CoSIM

Jump to solution

Hello!

I've implemented a Convolutional Neural Network in HLS and I'm wondering why there is a large difference between reported Synthesis Latency and Co-Simulation Latency. 

Synthesis reports 2664575 Clock Cycles while Co-Sim reports 6712380.

The Synthesis Latency is the one I would expect when theoretically calculating the latency of the different layers. 

When I run the Network on-board I also get the Co-Sim Latency. 

What does Co-Sim take into account that Synthesis doesn't? I've read that it also simulates AXI-Master accesses, so I changed the bit-width of my input and output to test if it changes something, but latency stays the same. Is there something else Co-Sim additionally simulates?

Best regards 

Jonas

0 Kudos
1 Solution

Accepted Solutions
j_ney
Contributor
Contributor
613 Views
Registered: ‎11-26-2017

In my case the solution to the problem was the depth of the HLS streams. 

I've implemented a design with dataflow between functions and using higher depth for the streams between functions, I can achieve the latency given by synthesis. 

It seems like synthesis assumes infinite FIFO depth for the latency calculation. 

Best regards

Jonas

View solution in original post

0 Kudos
2 Replies
nithink
Xilinx Employee
Xilinx Employee
658 Views
Registered: ‎09-04-2017

@j_ney The latency values provided after c-synthesis are static values based on the shortest and longest path in the design. The values shown after co-sim are the values based on the simulation data set and are the actual values which you need to look at

Thanks,

Nithin

0 Kudos
j_ney
Contributor
Contributor
614 Views
Registered: ‎11-26-2017

In my case the solution to the problem was the depth of the HLS streams. 

I've implemented a design with dataflow between functions and using higher depth for the streams between functions, I can achieve the latency given by synthesis. 

It seems like synthesis assumes infinite FIFO depth for the latency calculation. 

Best regards

Jonas

View solution in original post

0 Kudos