08-31-2018 08:41 AM
I was trying to synthesize a function which uses floating point variables. Synthesis result includes some .tcl files as ips.
I want to have the whole design as verilog code and be able to use it outside Xilinx tools environment. I wanted to know is there any way I can see the verilog code of these known ips? Or is there any way I can force to generate everything in verilog rather than using these ip cores?
09-07-2018 04:48 AM
Are you using HLS and providing inputs in for of C/C++?
After you export IP, it is recommended to use the IP by adding the .zip file(generated in the impl/ip folder of HLS Project) to the IP repository, hence using the .xci and .xml. But you can try adding the RTL files generated after C-synthesis to the third party synthesis tool. However, this process is not recommended.
09-07-2018 07:52 AM - edited 09-07-2018 07:52 AM
I am using vivado HLS and providing C/C++ code and its input file is also included.
Actually I don't want to export any new IPs, I use the regular synthesis flow and automatically it generated some parts using pre-defined floating point ip cores from Xilinx. It only shows the .tcl file under syn/verilog. My problem is I need to have the whole thing in verilog so that I am able to synthesize it in a different environment. The question is is there any way I can get the whole design in verilog files rather than .tcl ? If not, is there any way to force Vivado HLS not to use any pre-defined ip ?
09-07-2018 06:57 PM
@atefeh.mehrabi No, it's not possible.
HLS doesn't actually know how to implement floating-point operations; it relies completely on the separate floating point IP core. It has no way to implement your floating-point maths internally.
With that said, if you were hoping to use this in a different environment for a non-Xilinx chip, I would advise you to send a copy of the licensing agreement (that you agreed to when installing Vivado) over to your lawyer first. HLS (and VIvado) is licensed for Xilinx devices only, and development costs on this sort of thing are high enough that ignoring licensing terms is a very bad idea.
09-08-2018 09:22 AM
Thanks for your response.
I think I did not make my point clear. Yes, I need the whole design in verilog but not because I want to program a device different from Xilinx devices. I only use simulation not actual device programming. Even if you want to look at your waves in e.g. Modelsim or any other analysis tool outside vivado hls you need to provide all modules in verilog and because these ips are not provided in verilog it cannot work. That's why I am asking is there any way to extract the verilog file for the used floating point ips from provided .tcl files ? Can I do anything after synthesis to add used verilog files to the reports rather than only describing them in .tcl format?
09-11-2018 08:05 AM
09-11-2018 08:12 AM
Yes, that's true. I am using it only for Xilinx devices.
My question was sth else. I was asking is it possible to see the verilog code of the used floating point ip cores after synthesis instead of seeing only .tcl scripts? I mean inside vivado HLS and for xilinx FPGAs.
09-12-2018 04:04 AM
@atefeh.mehrabi You can't.
The floating-point IP core is encrypted, mainly to stop people poking around at the internal Verilog/VHDL/schematics inside there.
I expect that Xilinx will sell you an unencrypted version if you ask. The cost of this is likely to be at least five figures, possibly six.