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maps-mpls
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Mentor
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Registered: ‎06-20-2017

Question I need answered before adopting Vitis HLS

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In Vivado HLS, I can make an arbitrarily sized AXIS interface (%8).

How do I do this in Vitis HLS?  Vitis HLS ignores my size specification and makes an 8-bit AXIS interface regardless of what I specify?

*** Destination: Rapid design and development cycles *** Please remember to give internet points to those who help you here. ***
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p27803
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Registered: ‎03-31-2017
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p27803
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Registered: ‎03-31-2017
maps-mpls
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Mentor
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Registered: ‎06-20-2017

Thanks, it has an answer, but I am going to pass on that and use Vivado HLS for now.  Vivado HLS is working so I guess I'll try Vitis HLS the next time I install the latest releases from Xilinx (probably within a month or two).  I don't have time to install the latest right now as I am on a project and need to make progress.

*** Destination: Rapid design and development cycles *** Please remember to give internet points to those who help you here. ***
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