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Anonymous
Not applicable
3,745 Views

Register values are not in the post co/sim wave form

Hello,

I would like to see the values of all the arguments that are in the header function, but only see the axi_light signals and block control signals. How do I add the information about the variables, so I could see their values at each clock cycle? I am interested in *focus and *position variables.

void RB_FOCUS(
		hls::stream<RAW_PIXEL> &inStream,
		int *focus,
		int *position,
		int rows,
		int cols,
		int xo,
		int yo,
		int x,
		int y,
		int istep,
		int idfmax,
		ap_uint<1> infocus,
		ap_uint<1> outrnge){

 

Capture.PNG

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-17-2011

hi @Anonymous

 

this is not what you expect.

from your screenshot it appear you put those arguments on the AXI-Lite interface.

those will be sampled/stored at the beginning of the run of the IP and might be updated back later.

you will not be able to see those variables taking multiple values over time - basically you'll have to trace through all the derived values. eg your code is f=*focus; f+=1; f*=3; *focus=f; would be implemented as something like f1=*focus_input; f2=f1+1; f3=f2*3; *focus_output=f3;

 

in the simulation that you have you can check where are the write or read transactions for those AXI lite registers. for example, they might have addresses 16=0x10 and 20=0x14 ; to know the addresses you need to check the axilite adaptor verilog or VHDL generated code. we don't copy those details in reports.

 

- Hervé

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Anonymous
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@herver Hello,

in the simulation that you have you can check where are the write or read transactions for those
AXI lite registers. for example, they might have addresses 16=0x10 and 20=0x14 ;
to know the addresses you need to check the axilite adaptor verilog or VHDL generated code.
we don't copy those details in reports.

I still can not understand how I can monitor the values of *focus and *position. Would it be possible to know the values at least after each function call (not every clock cycle) in HLS C/RTL simulation?

#pragma HLS INTERFACE ap_none port=outrnge
#pragma HLS INTERFACE ap_none port=infocus
#pragma HLS INTERFACE ap_stable port=istep
#pragma HLS INTERFACE ap_stable port=idfmax
#pragma HLS INTERFACE ap_stable port=y
#pragma HLS INTERFACE ap_stable port=x
#pragma HLS INTERFACE ap_stable port=yo
#pragma HLS INTERFACE ap_stable port=xo
#pragma HLS INTERFACE ap_stable port=cols
#pragma HLS INTERFACE ap_stable port=rows

#pragma HLS INTERFACE s_axilite port=idfmax bundle=CONTROL
#pragma HLS INTERFACE s_axilite port=istep bundle=CONTROL
#pragma HLS INTERFACE s_axilite port=y bundle=CONTROL
#pragma HLS INTERFACE s_axilite port=x bundle=CONTROL
#pragma HLS INTERFACE s_axilite port=yo bundle=CONTROL
#pragma HLS INTERFACE s_axilite port=xo bundle=CONTROL
#pragma HLS INTERFACE s_axilite port=cols bundle=CONTROL
#pragma HLS INTERFACE s_axilite port=rows bundle=CONTROL
#pragma HLS INTERFACE s_axilite port=position bundle=CONTROL
#pragma HLS INTERFACE s_axilite port=focus bundle=CONTROL
#pragma HLS INTERFACE axis port=inStream
#pragma HLS INTERFACE s_axilite port=return bundle=CONTROL

Also, the two variables are declared the same way in the function header (see the original post), and also have the same directives in the HLS project, but when the IP drivers are generated for SDK, the variable registers have different sets of functions:

XRb_focus_Get_focus()
XRb_focus_Get_focus_vld()


XRb_focus_Set_position_i()
XRb_focus_Get_position_i()
XRb_focus_Get_position_o()
XRb_focus_Get_position_o_vld()

So, it looks like I can not write to focus. Also, why do I have position_i and position_o as two different registers? Is it not possible to write and read from the same register? For some reason, the infocus and outrnge are created as inputs to the IP, and I want them to be simple wire outputs. How do I fix all these problems?

Thank you.

 

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Xilinx Employee
Xilinx Employee
3,623 Views
Registered: ‎08-17-2011

hi @Anonymous

 

position is probably an input and an output in your code so there is the need for 1 register per direction.

focus is probably only output

 


For some reason, the infocus and outrnge are created as inputs to the IP, and I want them to be simple wire outputs. How do I fix all these problems?

 

That doesn't make sense.. if they are inputs they can't be outputs/. if you read from them in the C code they are input to the IP. they will never output ports of the IP: you need to change your C code.

- Hervé

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* Readme/Guidance* http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

* Please mark the Answer as "Accept as solution" if information provided is helpful.
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Anonymous
Not applicable
3,621 Views

@herver I see, but I only write to infocus and to outrnge in my C code, should I change the header file to to the pointers *infocus and to *outrnge to make them outputs only?

 

I still can not understand how I can monitor the values of *focus and *position. Would it be possible to know the values at least after each function call (not every clock cycle) in HLS C/RTL simulation?

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