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Adventurer
Adventurer
2,101 Views
Registered: ‎08-07-2014

Resetting a generated HLS module

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Hello,

 

I've developed a small HLS module that is doing a simple math computation. Basically it has an accumulator and an output that is the accumulator division by another number. Both input and output are AXI-S interfaces. An ap_ctrl interface is created (inferred) and I can successfully start it, send data, read output and wait for ap_done and start the process all over again.

 

My problem is if I increase the frequency of operations (i.e. setting ap_start, send data, read output, wait for ap_done), the HLS module stalls.... not rising ap_done anymore. I took care of that the number of operations per second (frequency of operations) doesn't violate the estimated module max latency (37 clock cycles) and max interval (38 clock cycles).

 

So, I'm about to test resetting the entire module when it hangs. My question is: how many clock cycles ap_rst_n should be asserted to completely propagate reset in the HLS module? Is there a minimum clock cycles? Or is there any way to discover this number?

 

regards

 

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Adventurer
Adventurer
2,523 Views
Registered: ‎08-07-2014

I got the problem fixed by creating an 'command' port that, as a predefined 'command' is written to, clears all internal variables. So the core itself isn't being reset (by asserting ap_rst_n), but internal registers are being cleared.

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Scholar
Scholar
2,086 Views
Registered: ‎03-22-2016

@brasilino Each HLS component is synthesized for a given frequency, Which is set in Solution Settings/ Synthesis/ Period . If You increase your design frequency in Vivado without adjusting in HLS again you will have a timing violation.

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Adventurer
Adventurer
2,054 Views
Registered: ‎08-07-2014

@hbucher,

 

thanks for your reply. Maybe I wasn't clear, but the frequency of operations I mentioned isn't the clock frequency, but the number of operations done by the HLS module in a given time.

 

An operation, in this context, would be setting ap_start, send data, read output, wait for ap_done (written in parenthesis in my previous post). Each operation takes many hundred of clock cycles to complete.

 

But, anyway, the problem is that after around 250 operations the module stalls, not rising ap_done anymore.

 

regards

 

Adventurer
Adventurer
2,524 Views
Registered: ‎08-07-2014

I got the problem fixed by creating an 'command' port that, as a predefined 'command' is written to, clears all internal variables. So the core itself isn't being reset (by asserting ap_rst_n), but internal registers are being cleared.

View solution in original post

Explorer
Explorer
2,017 Views
Registered: ‎08-31-2017

@brasilino 

 

 Do you mean you implement such clear method in HLS code ?

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Adventurer
Adventurer
2,015 Views
Registered: ‎08-07-2014

@nanson

 

Yes... pretty easy. Create a 'cmd' (command) input port that when a certain "opcode" is written to it, you

zero all internal (static) variables on your design. It worked for me.

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