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Observer pcross
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Registered: ‎11-14-2018

Simulating m_axi interface with offset=direct

I am attempting to pipeline a design which both reads and writes on a single m_axi interface at the same time. This is possible for the interface but due to some weird limitation documented here https://forums.xilinx.com/t5/Vivado-High-Level-Synthesis-HLS/Concurrent-AXI-read-and-write/td-p/852229 I must create 2 seperate interfaces and then bundle them together. Annoyingly this only works if the offset is set to either direct or slave.

 

Since I really only want 1 interface and have created the second one strictly to help HLS along I would like these 2 interfaces to have the same offset. I'm concerned whether or not the RTL design will freak out if I set them both to say 0 (effectively off), so I want to simulate the behaviour using a testbench. I have a functioning testbench where I create 1 array and pass it as the input for both m_axi interfaces but when I look at the output I notice that one of my interfaces has an offset of 0x0004_0000 applied to it. Is there any way for me to control the offsets via the testbench? I feel like this is something that should be supported but I cannot find any documentation explaining how to do it. 

Thank you.

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