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[Synthesizability check failed] multiple begin anchors

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Visitor
Posts: 8
Registered: ‎08-02-2017

[Synthesizability check failed] multiple begin anchors

Hi,

 

I have encountered a weird vivado_hls error. It only reports:

 

ERROR: [HLS 200-70] Synthesizability check failed.
command 'ap_source' returned error code
        while executing
"source [lindex $::argv 1] "
        ("uplevel" body line 1)
invoked from within
        "uplevel \#0 { source [lindex $::argv 1] } "

Before it, there is a warning:

 

WARNING: Region "hls_label_2" has multiple begin anchors.

So what is the possible reason for this error?

 

Thanks,

troore

Voyager
Posts: 1,364
Registered: ‎06-24-2013

Re: [Synthesizability check failed] multiple begin anchors

Hey @troore,

 

I have encountered a weird vivado_hls error.

Create a (minimal) test case and upload it.

 

So what is the possible reason for this error?

Most likely a bug in HLS.

Hard to tell without source code.

 

Best,

Herbert

-------------- Yes, I do this for fun!
Visitor
Posts: 8
Registered: ‎08-02-2017

Re: [Synthesizability check failed] multiple begin anchors

I'm so sorry for the inconvenience, @hpoetzl. That is not a small design. But I think I've located the point where this error happens. I just paste the code snippet below:

 

int read_idx = 0;
bool flag = true;

for (int i1 = 0; i1 < BS_I; i1++) // BS_I==2
#pragma HLS UNROLL
for (int r1 = 0; r1 < BS_R; r1++)
#pragma HLS UNROLL
for (int o1 = 0; o1 < BS_O; o1++)
{
#pragma HLS UNROLL
    // some unrelated computation
    // ...

    read_idx++;
    if (read_idx == (BS_R * BS_O))
        flag = false;
}

And the "has multiple begin anchors" happens at the line (the "{") just below the "o1" loop. I've somewhat explored it, and found several interesting things:

 

1. if "BS_I==1", this error disappears;

 

2. if I remove

 

 read_idx++;
 if (read_idx == (BS_R * BS_O))
    flag = false;

this error disappears too;

 

3. If I manually flatten the "(i1,r1,o1)" loop, as follows:

 

int i1 = 0;
int r1 = 0;
int o1 = 0;
for (int i = 0; i < (BS_I * BS_R * BS_O); i++)
{
#pragma HLS UNROLL
    // original code
    
    o1++;
    if (o1 == BS_O)
    {
        r1++;
        if (r1 == BS_R)
        {
            i1++;
            if (i1 == BS_I)
                i1 = 0;
        }
    }
}

HLS also passed. So I am still not sure what causes this error.

 

Thanks,

troore

 

Xilinx Employee
Posts: 528
Registered: ‎08-17-2011

Re: [Synthesizability check failed] multiple begin anchors

hi @troore

 

your curly brace in the snippet seems wrong, you should have at least 3 regions so that the unroll pragma can be in that region.

maybe jsut a typo in the snippet.

 

unrolling all the loops isn't the best. it will create parallel HW alright but now you need to feed parallel data to this and i don't think that's what you do: it looks all sequential - maybe i'm wrong.

 

maybe remove the unrolls and pipeline the innermost loop, the other outer loops should be flatten automatically.

- Hervé

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Visitor
Posts: 8
Registered: ‎08-02-2017

Re: [Synthesizability check failed] multiple begin anchors

Thanks for your reply, @herver. Yeah, it is really a typo as I forgot the reinitialization, lol. The correct code should be:

o1++;
if (o1 == BS_O)
{
    o1 = 0;
    r1++;
    if (r1 == BS_R)
    {
        r1 = 0;
        i1++;
        if (i1 == BS_I)
            i1 = 0;
    }
}

I have to UNROLL all of them as actually there is an outer loop outside this loop, and with this loop there is another loop at the same level. If I want to pipeline the outer loop, I have to do UNROLL on it.

 

I will consider your suggestions in detail. Thanks again!

 

troore