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Adventurer
Adventurer
6,885 Views
Registered: ‎12-23-2012

Timing mismatch of Pcore generated by Vivado_hls when running on the board

Hi, all,

   I am using Vivado_hls to generate my Pcore. I check its timing on modelsim, everything is ok. However, when I put it on EDK and using ChipScope to trigger the internal signals of my Pcore, it shows that my Pcore behaves wrong. The input data to the Pcore is correct, but the output is wrong.

 

   I have pass another Pcore on EDK, and this Pcore has the same interface with the one above, and the software part to control the Pcores is the same. So my software part is correct (The result of ChipScope also proves this point).

 

   Could anyone offer me any directions?

   Thanks.

Henry

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Moderator
Moderator
6,850 Views
Registered: ‎04-17-2011

Are the latency numbers in your HLS Synthesis Report file as per your expectations? Also, are you seeing any timing violations after including chipscope in your project?
Regards,
Debraj
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Adventurer
Adventurer
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Registered: ‎12-23-2012

Hi, Debrajr,

>Are the latency numbers in your HLS Synthesis Report file as per your expectations?

  Yes, the latency is what I expect.

  One thing is weird that the Vivado_hls C/RTL Co-simulation gives me error and fails in the co-sim; However, when I dump trace and using modelsim to check my design, the input and output data are exactly what I want. Maybe there is a bug when the Vivado hls tries to read from the result writen by modelsim. I have no idea about that. This problem is also happened on my last design which is successfully running on Zedboard.

 

>Also, are you seeing any timing violations after including chipscope in your project?

  My design is used PlanAhead to generate the bit stream. And the "Implemented Timing report" shows that the design has met all the constratints (no timing violations) and it can achieve 100 MHz. I just use 50 MHz for my design.

  I only use the ChipScope to check my input/output to the hardware IP and the interface protocol of the hardware IP. I can see from the ChipScope that the input data and the interface protocol are correct; However, when I check my output data from the hardware IP, the result is wrong. Because the Verilog source code of the hardware IP generated by the Vivado hls is not human-readable. It is quite hard to using the ChipScope to debug where the internal problem is. 

  Do you have any suggestion? I don't have a webcase account, so I can not report my problems on the webcase.

 

  I am using Zedboard, Xilinx ISE Design suite 14.5 and Vivado_hls 2013.2

 

Thanks for your attention.

Henry

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Moderator
Moderator
6,822 Views
Registered: ‎04-17-2011

Hi, Debrajr,

>Are the latency numbers in your HLS Synthesis Report file as per your expectations?

  Yes, the latency is what I expect.

  One thing is weird that the Vivado_hls C/RTL Co-simulation gives me error and fails in the co-sim; However, when I dump trace and using modelsim to check my design, the input and output data are exactly what I want. Maybe there is a bug when the Vivado hls tries to read from the result writen by modelsim. I have no idea about that. This problem is also happened on my last design which is successfully running on Zedboard.

 

Debrajr: This may be an issue with the tool. Do you mean that the RTL Cosim failed but you had set dump trace option and once you opened the .vcd file, you can see that the input and ouput data are as per your expectation. Would you PM your project and also let us know the signals of intrest so that we can check?

 

>Also, are you seeing any timing violations after including chipscope in your project?

  My design is used PlanAhead to generate the bit stream. And the "Implemented Timing report" shows that the design has met all the constratints (no timing violations) and it can achieve 100 MHz. I just use 50 MHz for my design.

  I only use the ChipScope to check my input/output to the hardware IP and the interface protocol of the hardware IP. I can see from the ChipScope that the input data and the interface protocol are correct; However, when I check my output data from the hardware IP, the result is wrong. Because the Verilog source code of the hardware IP generated by the Vivado hls is not human-readable. It is quite hard to using the ChipScope to debug where the internal problem is. 

 

  Do you have any suggestion? I don't have a webcase account, so I can not report my problems on the webcase.

 

Debrajr: So you exported the RTL as IP format and added it to PlanAhead? Did you run Post Implementation Simulation so that you can debug the issue locally and not restore to using chipscope?

 

  I am using Zedboard, Xilinx ISE Design suite 14.5 and Vivado_hls 2013.2

 

Thanks for your attention.

Henry

Regards,
Debraj
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Highlighted
Adventurer
Adventurer
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Registered: ‎12-23-2012

Hi, Debraj,

  Thanks for your reply.

 

>Debrajr: This may be an issue with the tool. Do you mean that the RTL Cosim failed but you had set dump trace option and once you opened the .vcd file, you can see that the input and ouput data are as per your expectation. Would you PM your project and also let us know the signals of intrest so that we can check?

 

  Yes. I set dump trace option and check the *.wlf file with modelsim. It has the same problem with the file I sent you last time (The email named "Vivado HLS C/RTL Cosimulation_henry"). However, I am unlucky this time. I can not pass this design on the real hardware due to the problem I report on this thread. I will PM you the file. Thanks. :-)

 

>Debrajr: So you exported the RTL as IP format and added it to PlanAhead? 

  Yes, you are right. I use the Pcore generated by Vivado hls on real hardware platform (ZC702 and zedboard).

 

>Did you run Post Implementation Simulation so that you can debug the issue locally and not restore to using chipscope?

  Because you know, my Pcore is attached to AXI interconnect bus, I need  to write testbench to send the data through the bus and I don't know how to write the testbench to communicate my hardware IP via AXI interconnect bus. Could you give me any reference design on Post Implementation Simulation or any links? 

 

Best regards,

Henry

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