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lums_123
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Registered: ‎07-22-2018

Unable to satisfy pipeline directive: Function contains subloop(s) not being unrolled.

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Hi,

I have a written a very simple loop which extracts 2-bit values out of two ap_int<512> variables, multiplies the values together, and stores the results in another ap_int<512>. Extraction of 2-bit values is done as (BITS_PER_VAL=2):

inline ap_int<BITS_PER_VAL> get_binval(ap_int<512> map, int index){
	return map.range((index+1)*BITS_PER_VAL-1, index*BITS_PER_VAL);
}

 Multiplication loop is defined as:

ap_int<512> aa, bb, cc;
//Populated aa and bb here
mul_loop: for (int i = 0; i < 256; i++){
	#pragma HLS PIPELINE II=1
	put_binval(&cc, get_binval(aa, i)*get_binval(bb, i), i);
}

Where put_binval is defined as:

inline void put_binval(ap_int<512> *map, ap_int<BITS_PER_VAL> val, int index){
	map->range((index+1)*BITS_PER_VAL-1, index*BITS_PER_VAL) = val;
}

When I synthesize this in Vivado HLS 2015.4, I get a warning that says "@W [SCHED-65] Unable to satisfy pipeline directive: Function contains subloop(s) not being unrolled." and my mul_loop is not pipelined. Could you kindly look at my code and guide me on how I would go about pipelining this loop? I'd be happy to share the full source with you.

Best Regards,

 

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calibra
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Registered: ‎06-20-2012
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'mul_loop'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [SCHED 204-11] Finished scheduling.

Sometimes programs improve with versions.

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calibra
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Include

#pragma HLS INLINE


into funtion get_binval and put_binval.

 

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lums_123
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Registered: ‎07-22-2018

Unfortunately this doesn't resolve my issue. Inlining was happening automatically without using this pragma anyways. So adding this pragma has no effect on pipelining. Here are the console messages that demonstrate this:

@I [XFORM-602] Inlining function 'get_binval' into 'xbnn' (xdnn.cpp:33) automatically.
@I [XFORM-602] Inlining function 'put_binval' into 'xbnn' (xdnn.cpp:35) automatically.

 

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calibra
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In version 2019.2  it is running fine.

Could you share the code ?

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lums_123
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Here's the entire source file. This forum is not allowing attachments. xbnn is the top function.

 

#include <stdio.h>
#include <ap_int.h>

#define BITS_PER_VAL 2

inline ap_int<BITS_PER_VAL> get_binval(ap_int<512> map, int index){
	#pragma HLS INLINE
	return map.range((index+1)*BITS_PER_VAL-1, index*BITS_PER_VAL);
}

inline void put_binval(ap_int<512> *map, ap_int<BITS_PER_VAL> val, int index){
	#pragma HLS INLINE
	map->range((index+1)*BITS_PER_VAL-1, index*BITS_PER_VAL) = val;
}

void xbnn(ap_int<512> *ifmap, ap_int<512> *kmap, ap_int<512> *ofmap){
	#pragma HLS INTERFACE m_axi depth=1 port=ifmap offset=slave bundle=gmem0
	#pragma HLS INTERFACE m_axi depth=1 port=kmap offset=slave bundle=gmem1
	#pragma HLS INTERFACE m_axi depth=1 port=ofmap offset=slave bundle=gmem0

	#pragma HLS INTERFACE s_axilite port=ifmap bundle=control
	#pragma HLS INTERFACE s_axilite port=kmap bundle=control
	#pragma HLS INTERFACE s_axilite port=ofmap bundle=control
	#pragma HLS INTERFACE s_axilite port=return bundle=control

	ap_int<512> aa, bb, cc;
	{
		#pragma HLS LOOP MERGE
		memcpy(&aa, ifmap, 64);
		memcpy(&bb, kmap, 64);
	}

	mul_loop: for (int i = 0; i < 512/BITS_PER_VAL; i++){
		#pragma HLS PIPELINE II=1
		put_binval(&cc, ap_int<BITS_PER_VAL>(get_binval(aa, i)*get_binval(bb, i)), i);
	}
	memcpy(ofmap, &cc, 64);
}

 

Thanks

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calibra
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INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'mul_loop'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 1.
INFO: [SCHED 204-11] Finished scheduling.

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lums_123
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Registered: ‎07-22-2018

Thanks. This is weird. I'll test on SDAccel or Vitis on Nimbix cloud.

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