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Visitor
Visitor
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Registered: ‎06-06-2018

Unable to specify ap_stable port in Vitis HLS 2020.1

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I am trying to specify a port type of "ap_stable" in Vitis HLS 2020.1, and I am having some difficulty doing so. Here is a contrived example of what I am trying to do:

#include "ap_int.h"

ap_uint<32> MultiplyThenXor(ap_uint<16> a, ap_uint<16> b, ap_uint<32> xorMask) {
#pragma HLS pipeline II=1
#pragma HLS INTERFACE ap_stable port=xorMask
	return (a * b) ^ xorMask;
}

 What I expect is that "xorMask" will be given an interface type of "ap_stable", and then no delay matching registers will be inserted. However, in the log I see that the interface type for "xorMask" is ap_none, not ap_stable:

INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'MultiplyThenXor' 
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-500] Setting interface mode on port 'MultiplyThenXor/a' to 'ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'MultiplyThenXor/b' to 'ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'MultiplyThenXor/xorMask' to 'ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on function 'MultiplyThenXor' to 'ap_ctrl_hs'.
INFO: [RTGEN 206-100] Generating core module 'mul_mul_16ns_16ns_32_4_1': 1 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'MultiplyThenXor'.

 And when I examine the generated HDL, I see that, contrary to my intention, delay matching registers have been inserted.

In Vivado HLS 2019.2, this example works as I expect: The port type is detected properly as ap_stable, and no delay matching register are inserted.

Was there a change in Vitis HLS 2020.1 in the treatment of ap_stable ports? What do I need to do to get an ap_stable port in Vitis HLS 2020.1?

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Visitor
Visitor
288 Views
Registered: ‎06-06-2018

Just got word from my Xilinx FAE that ap_stable was broken in Vitis HLS 2020.1, but it has been fixed in 2020.2.

View solution in original post

3 Replies
Moderator
Moderator
351 Views
Registered: ‎11-21-2018

Hi @jcreighton 

From looking at the Vitis HLS user guide:

https://www.xilinx.com/html_docs/xilinx2020_1/vitis_doc/programmingvitishls.html

 

It seems that the ap_stable type can only be applied to input ports. When applied to inout ports, only the input of the port is considered stable.

From the code you provided, it looks like you are not just using ap_stable as an input port? Please correct me if I'm wrong and I can look into this in some more detail. 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor
Visitor
289 Views
Registered: ‎06-06-2018

Just got word from my Xilinx FAE that ap_stable was broken in Vitis HLS 2020.1, but it has been fixed in 2020.2.

View solution in original post

Moderator
Moderator
246 Views
Registered: ‎11-21-2018

Hi @jcreighton 

Thanks for following this up with your solution. I only just heard about this bug as well. 

Regards

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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