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Use case for AXI-Stream with side-channels

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Hi, dear HLS elites,

 

 I'm studying the HLS interface synthesis for AXI interface now. For AXI-Stream, I have some simple questions related to the use case. Appreciate for your any comments.  Thanks

 

Q1: For application like line buffer of image video or ping-pong buffer mechanism, is it good fit to use AXI-stream ?

 

Q2: In HLS, it also supports AXI-Stream with side-channels. However, I don't understand the benefit or use case to use such feature. Would you please illustrate the example you know ? 

 

Q3: Since AXI-4 stream is a kind of sequential streaming transaction, what AXI burst length does it use in general which appears not mentioned in UG902 ? 

 

Q4: What's the downside of AXI4-stream in your experience such as limitation of requirement of throughput or latency for target applications ?

 

All the best,

Nan-Sheng

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Registered: ‎08-31-2017

Re: Use case for AXI-Stream with side-channels

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@hbucher  First, thanks for your patient to share with me on the post. However, I have some follow up questions below.

 

I'm not familiar with TUSER and need some study.

 

For some applications with real-time constraints, it requires to calculate the worst case of preparing for the data for operation in advance. Also, for traffic moving over the on-chip bus, if one master occupies the bus for too long time period, it might hurt other modules with hard real-time constraints. Thus, for worst-case analysis of the capability of on-chip bus design, it needs to model the capability of masters and slave for ESL level emulation/simulation/analysis as we did in ASIC development. That's why I asked these questions on the AXI-stream before I can well use.

 

As you explained the implementation of AXI-stream doesn't use BURST protocol and only be with an address with every data transfer, what if it doesn't meet the requirement of worst-case latency expected, what can user do then ? To change with AXI master ?

 

It seems to me that if the requirement of throughput and latency is not so strict, it is a must to use to facilitate the development. 

 

Thanks

 

All the best,

Nan-Sheng

 

 

 

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Re: Use case for AXI-Stream with side-channels

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@nanson  

 

Q1: as long as it fits the performance requirements, why wouldn't it be? AXI will deliver one word at every clock cycle so there is no waste. With the advantage that you have the entire Vivado ecosystem to ease things for you.

 

Q2: By "side channels" you mean TUSER only or TKEEP/TSTRB/TID/TDEST? 

 

Generally, Xilinx IP uses the TUSER field only to augment the TDATA field with information that could prove useful, but ultimately can be ignored. Ignoring TUSER could result in some loss of information, but the TDATA field still has some meaning. For example, an FFT core implementation could use a TUSER output to indicate block exponents to apply to the TDATA bus; if TUSER was ignored, the exponent scaling factor would be lost, but TDATA would still contain un-scaled transform data

 

axi_side_channels.png

 

Q3: Burst dramatically augments performance in AXI protocol by removing the need to send an address with every data transfer. As AXI-stream has no concept of addresses, it does not apply.

 

Q4: AXI Stream is a very simple protocol as is Avalon-ST. There are features that are different like multi-channel support but nothing that will actually be detrimental to a project. I am currently doing a project of acceleration of financial transactions in 40G and I am using AXI stream everywhere. It is a breeze - fully supported, easy to simulate in code. 

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Registered: ‎08-31-2017

Re: Use case for AXI-Stream with side-channels

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@hbucher  First, thanks for your patient to share with me on the post. However, I have some follow up questions below.

 

I'm not familiar with TUSER and need some study.

 

For some applications with real-time constraints, it requires to calculate the worst case of preparing for the data for operation in advance. Also, for traffic moving over the on-chip bus, if one master occupies the bus for too long time period, it might hurt other modules with hard real-time constraints. Thus, for worst-case analysis of the capability of on-chip bus design, it needs to model the capability of masters and slave for ESL level emulation/simulation/analysis as we did in ASIC development. That's why I asked these questions on the AXI-stream before I can well use.

 

As you explained the implementation of AXI-stream doesn't use BURST protocol and only be with an address with every data transfer, what if it doesn't meet the requirement of worst-case latency expected, what can user do then ? To change with AXI master ?

 

It seems to me that if the requirement of throughput and latency is not so strict, it is a must to use to facilitate the development. 

 

Thanks

 

All the best,

Nan-Sheng

 

 

 

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Re: Use case for AXI-Stream with side-channels

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@nanson I think you are mixing AXI and AXI stream. These are two different protocols. The first is memory mapped, transactions have data and address. The later has only data. 

The worst case scenario is pretty much independent on the axi-stream protocol. As long as TREADY and TVALID are asserted, a transfer is done. In case of +10G network streams, there is not even a TREADY signal.  It depends on the receiver to be ready to accept data and on the sender to be ready to send data. The protocol itself has zero latency in that sense.

 

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Re: Use case for AXI-Stream with side-channels

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@hbucher Thanks for the clarification. I got it now.

 

 Does it mean AXI-STREAM is a good fit for point-to-point communication on-chip instead of pass through shared bus infrastructure ?

 

Thanks

 

All the best,

Nan-Sheng

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Re: Use case for AXI-Stream with side-channels

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@nanson You see, a shared bus only makes sense if you have address to discern which route the data will take. 

In AXI stream you have kind of the same with AXI STream interconnect (where TDEST is required). The AXI STream interconnect allows you to prioritize traffic based on TDEST. The default algorithm is round robin but you can assign static priorities so your critical path will have the highest priority always.

 

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Re: Use case for AXI-Stream with side-channels

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@hbucher  I see, thanks. One more last question : if that's the case, I'm curious if the Xilinx's infrastructure IP  does support both protocol of AXI and AXI-stream transaction. Or they use different infrastructure IP when integration.  Thanks

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Re: Use case for AXI-Stream with side-channels

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Hello,

 

I thought I would try to answer the last question here.

 

The main reference guide for the Vivado AXI IP can be found here:

https://www.xilinx.com/support/documentation/ip_documentation/axi_ref_guide/latest/ug1037-vivado-axi-reference-guide.pdf

 

Page 82 talks about the AXI4-Stream adoption and support. 

 

And, we have two different IP's for the different interconnect types, so the structure is different as you thought:

https://www.xilinx.com/products/intellectual-property/axi4-stream_interconnect.html

https://www.xilinx.com/products/intellectual-property/axi_interconnect.html

 

In fact, the second IP explicitly states that the stream interface is not supported in that IP - which makes sense as streaming it is not a memory mapped interface as @hbucher mentioned.   

 

For more information on the HLS aspect of the side-channel signals in AXIS, look on page (109) here:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug902-vivado-high-level-synthesis.pdf

 

OK, I know this is a lot of information resources, but hopefully this helps.

 

Thank you,
Scott