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celestials
Observer
Observer
19,353 Views
Registered: ‎05-14-2014

Using array inputs and outputs on HLS with AXI interface

Hello all,

I want to generate a custom IP in Vivado HLS that in its top function includes arrays as inputs and outputs.

I have viewed the document ug902, and choos ap_hs as RTL interface and AXI4 Lite as Bus interface.

 

What is not clear to me is how the function is used in sdk correctly to get or set all the values the port expects. What should I do? Can you give me some example or any good suggestion?

 

---------------------------------------------------------------------------------------------------------

Here is my top function

void encrypt(unsigned char plaintext[16], unsigned char cryphttext[16]);

---------------------------------------------------------------------------------------------------------

 

Thank you!

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19 Replies
debrajr
Moderator
Moderator
19,339 Views
Registered: ‎04-17-2011

Refer chapter-10 of the tutorial: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_4/ug871-vivado-high-level-synthesis-tutorial.pdf
Regards,
Debraj
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celestials
Observer
Observer
19,330 Views
Registered: ‎05-14-2014

Thanks for your reply. I have looked into ug871 and found that the example set parameters in this way

------------------------------------------------------------------------------------

XHls_macc_SetA(&HlsMacc, a);
XHls_macc_SetB(&HlsMacc, b);
XHls_macc_SetAccum_clr(&HlsMacc, 1);

------------------------------------------------------------------------------------

However, the set function looks like void XHls_macc_SetA(XHls_macc *InstancePtr, u32 Data), both for the array and interger. (*InstancePtr is the instance, Data is the value to set) So how can I set the whole array into port?

Hope for your reply:)

Thanks! 

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debrajr
Moderator
Moderator
19,321 Views
Registered: ‎04-17-2011

If you have any array in the function then by default it is implemented as ap_memory. If not then you can specify as ap_memory.
Regards,
Debraj
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celestials
Observer
Observer
19,307 Views
Registered: ‎05-14-2014

Thanks for your reply. I'm a beginner for the ZYNQ board. It seems difficult for me to fix all the details. Can you show me some tutorials or just give me some example project. Then it may be easy for me to solve the problem. Now I have exported the IP from HLS using ap_memory interface.

=========================================================================

this is my top function: void encrypt(unsigned char plaintext[16]);

this is my directives settings: 

set_directive_resource -core RAM_1P "encrypt" plaintext
set_directive_resource -core AXI4LiteS -metadata "-bus_bundle encrypt_io" "encrypt" return

=========================================================================

So how to connext this block design in the Vivado and how to program in the SDK?

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debrajr
Moderator
Moderator
19,293 Views
Registered: ‎04-17-2011

Did you have a look at 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug871-vivado-high-level-synthesis-tutorial.pdf ?

Regards,
Debraj
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zaklah
Visitor
Visitor
19,277 Views
Registered: ‎05-21-2014

Dear Degrads;

I followed the tutorial "Streaming data between the Zynq CPU and HLS Accelerator Blocks" in ug871, but I am receiving this error message during Synthesis: "5] XIT evaluation error: File writer encountered an error: ../Using_IP_with_Zynq/lab2/project_2/project_2.srcs/sources_1/bd/design_1/ip/design_1_axis_subset_converter_0

_0/axis_subset_converter_v1_1/hdl/verilog/axis_subset_converter_v1_1_tdata_remap_design_1_axis_subset_converter_0_0.v"

 

Also, this warning message "

 [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified.
Please check your design and connect them if needed:
/RealFFT/xfft_0/s_axis_config_tdata
/RealFFT/xfft_0/s_axis_config_tvalid

 "

 

Thanks,

 

Zach

 

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dahenk
Explorer
Explorer
19,266 Views
Registered: ‎09-02-2013

"File writer encountered an error"

 

My guess is that your file path is too long. shorten the names of your folders or move the project up several levels.

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ywu
Xilinx Employee
Xilinx Employee
19,202 Views
Registered: ‎11-28-2007

That is very possible if you are running the tool on Windows, which has a 260 chars max for path names.

 

http://msdn.microsoft.com/en-us/library/windows/desktop/aa365247%28v=vs.85%29.aspx

 


@dahenk wrote:

"File writer encountered an error"

 

My guess is that your file path is too long. shorten the names of your folders or move the project up several levels.




Cheers,
Jim
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ywu
Xilinx Employee
Xilinx Employee
19,201 Views
Registered: ‎11-28-2007

The entire array will be memory mapped to AXI4 Lite slave interface as well. We generate drivers for the exported IP, which shows the memory offset for all registers including arrays. Below is an example. Note a memory port is mapped to a range of addresses at the bottom.

 

// BUS_A
// 0x0000 : Control signals
//          bit 0  - ap_start (Read/Write/COH)
//          bit 1  - ap_done (Read/COR)
//          bit 2  - ap_idle (Read)
//          bit 3  - ap_ready (Read)
//          bit 7  - auto_restart (Read/Write)
//          others - reserved
// 0x0004 : Global Interrupt Enable Register
//          bit 0  - Global Interrupt Enable (Read/Write)
//          others - reserved
// 0x0008 : IP Interrupt Enable Register (Read/Write)
//          bit 0  - Channel 0 (ap_done)
//          bit 1  - Channel 1 (ap_ready)
//          others - reserved
// 0x000c : IP Interrupt Status Register (Read/TOW)
//          bit 0  - Channel 0 (ap_done)
//          bit 1  - Channel 1 (ap_ready)
//          others - reserved
// 0x0010 : reserved
// 0x0014 : Data signal of b
//          bit 31~0 - b[31:0] (Read/Write)
// 0x0018 : reserved
// 0x001c : Data signal of c_i
//          bit 31~0 - c_i[31:0] (Read/Write)
// 0x0020 : reserved
// 0x0024 : Data signal of c_o
//          bit 31~0 - c_o[31:0] (Read)
// 0x0028 : reserved
// 0x002c : Data signal of flIn
//          bit 31~0 - flIn[31:0] (Read/Write)
// 0x0030 : reserved
// 0x0034 : Data signal of flOut_i
//          bit 31~0 - flOut_i[31:0] (Read/Write)
// 0x0038 : reserved
// 0x003c : Data signal of flOut_o
//          bit 31~0 - flOut_o[31:0] (Read)
// 0x0040 : Control signal of a
//          bit 0  - a_ap_vld (Read/Write/COH)
//          bit 1  - a_ap_ack (Read)
//          others - reserved
// 0x0044 : Data signal of a
//          bit 31~0 - a[31:0] (Read/Write)
// 0x1000 ~
// 0x1fff : Memory 'scale' (1024 * 32b)
//          Word n : bit [31:0] - scale[n]
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)

 

 

 

 

 

 


@celestials wrote:

Thanks for your reply. I have looked into ug871 and found that the example set parameters in this way

------------------------------------------------------------------------------------

XHls_macc_SetA(&HlsMacc, a);
XHls_macc_SetB(&HlsMacc, b);
XHls_macc_SetAccum_clr(&HlsMacc, 1);

------------------------------------------------------------------------------------

However, the set function looks like void XHls_macc_SetA(XHls_macc *InstancePtr, u32 Data), both for the array and interger. (*InstancePtr is the instance, Data is the value to set) So how can I set the whole array into port?

Hope for your reply:)

Thanks! 




Cheers,
Jim
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ribalda
Participant
Participant
14,350 Views
Registered: ‎06-16-2008

Hello Jim

 

Sorry for the bit off topic, but how do you manage to map an array into the axi lite bus?

 

I have tried with no luck to use the interface directive, and all I get is a ap_memory.

 

 

Regards!

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herver
Xilinx Employee
Xilinx Employee
14,336 Views
Registered: ‎08-17-2011

The answer is to use something similar to this:

 

void mytop(..., mydatatype myarray[MYWIDTH], ...)

#pragma HLS RESOURCE variable=myarray core=RAM_1P_BRAM metadata="-bus_bundle BUS_CTRL"
#pragma HLS INTERFACE ap_memory port=myarray

 

 

Please note and make sure it is understood that because the array is passed at the top level, the array is and must be initialized from the outside of the IP; in practice this in the C TB or embedded processor C code.

This feature is not supported by the new so-called "native AXI interface" directives that have been introduced with Vivado HLS 2014.1/.2; this feature will be supported in a future release.

 

This means that at the moment, the other directives need to use the same style:

#pragma HLS RESOURCE variable=return core=AXI4LiteS metadata="-bus_bundle BUS_CTRL"

 

I have created Xilinx Answer Record 61567 with this same answer (pending editorial edits) and a tiny example that runs the flow from a script; the example is intended to be used to see it "by yourself". This AR should be available within a few days from this post, and the link should be http://www.xilinx.com/support/answers/61567.htm

- Hervé

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franchesco
Newbie
Newbie
14,307 Views
Registered: ‎06-26-2014

How do I get around the [BD 41-759] warning message? It won´t let me perform synthesis.

 

Thank you in advance

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franchesco
Newbie
Newbie
14,297 Views
Registered: ‎06-26-2014

I was referring to this prior post over here:

 


@zaklah wrote:

Dear Degrads;

I followed the tutorial "Streaming data between the Zynq CPU and HLS Accelerator Blocks" in ug871, but I am receiving this error message during Synthesis: "5] XIT evaluation error: File writer encountered an error: ../Using_IP_with_Zynq/lab2/project_2/project_2.srcs/sources_1/bd/design_1/ip/design_1_axis_subset_converter_0

_0/axis_subset_converter_v1_1/hdl/verilog/axis_subset_converter_v1_1_tdata_remap_design_1_axis_subset_converter_0_0.v"

 

Also, this warning message "

 [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified.
Please check your design and connect them if needed:
/RealFFT/xfft_0/s_axis_config_tdata
/RealFFT/xfft_0/s_axis_config_tvalid

 "

 

Thanks,

 

Zach

 




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laursand
Contributor
Contributor
12,168 Views
Registered: ‎08-09-2013

hi Herve,

We are faced with a similar situation and wanted to confirm something... (using HLS 2014.4):

Our top HLS function has the following parameters:

 

void top_function(int param1, int param2, const short paramtable[1600], AXI_STREAM &src, AXI_STREAM &dst)

 

We are bundling these params (including the table) into 1 axilite bus interface with something like.

#pragma HLS interface axis port=src
#pragma HLS interface axis port=dst
#pragma HLS interface s_axilite bundle=coreconfig port=param1
#pragma HLS interface s_axilite bundle=coreconfig port=param2
#pragma HLS interface s_axilite bundle=coreconfig port=paramtable
#pragma HLS interface s_axilite bundle=coreconfig port=return

 

When looking at the generated driver header file, we see param1 mapped at offset 0x0010, param2 at 0x0018 then the paramtable mapped at 0x1000 onwards.

 

This paramtable seems to be implemented inside the core (the core shows that the coreconfig axi bus has 6 BRAMs). Accessing from firmware, we can read/write the table fine.

 

However, when we run the Core, we get different results than cosimulation (we double-checked that we are writing the same values as the TB). We are starting to think this is due to the way the table is read (by the Core) into local arrays used for processing.

 

As per your previous post (http://www.xilinx.com/support/answers/61567.htm), would it be better to implement a separate BRAM in Block Design and load it with the paramtable values? Or is the structure above handled by the HLS compiler? Specifically, it looks like the end of the table doesn't work right - maybe there is a maximum size for arrays passed as arguments?...

 

Thanks!

 

 

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herver
Xilinx Employee
Xilinx Employee
12,139 Views
Registered: ‎08-17-2011

Hi @laursand

 

please start a new thread as that's a new topic...

what you are doing should work and i can't see anything worng with your directives.

you imply that the issues you see are in the fpga system, so i assume that you have a processor. my gut feeling is that you have cache issues because your processor and IP don't seem to match as to what they are seeing (or do you have endianness problems??).

 

again, please start a new thread 

- Hervé

SIGNATURE:
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* Please mark the Answer as "Accept as solution" if information provided is helpful.
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laursand
Contributor
Contributor
12,138 Views
Registered: ‎08-09-2013

hi Herve,

I confirm what we have mentioned above actually works just fine.

The issue we had was with improper code (int/float type conversion) - somehow it simulated RTL correctly, but wasn't compiled the same in Vivado.

 

Thanks for your response though.. 

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shahid
Participant
Participant
9,673 Views
Registered: ‎03-25-2016

Hello celestials,

 

Did you solved your problem? How to pass array to IP in SDK? I am facing same problem. Can you please help me.

 

 

waiting for your reply.

Thanks

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monia
Visitor
Visitor
6,160 Views
Registered: ‎06-25-2018

hello Shahid,

Did you solved your problem?

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goldshakil
Observer
Observer
2,243 Views
Registered: ‎11-03-2019

I am facing the issue currently and I can't seem to find the answer.
Please help me out.
I have already checked chapter 10 and it seems it deals with integers. However when I changed the variables to array types then there is no Get OR set function. Instead there is XXX_Read_XXX_Words and XXX_Write_XXX_Words

 

here is the definition:
u32 XDahab_Read_out_r_Words(XDahab *InstancePtr, int offset, int *data, int length);
u32 XDahab_Write_out_r_Bytes(XDahab *InstancePtr, int offset, char *data, int length);


can you guide me on how to use them?

Please help me out thank you so much!

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