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378 Views
Registered: ‎04-25-2018

Vitis HLS generating bad HDL for hls::fir

I have a design that uses hls::fir, that works fine in Vivado HLS 2019.1, but when using Vitis HLS 2020.2 the generated VHDL has compilation errors:

ERROR: [VRFC 10-664] expression has 8 elements ; expected 24 [hls_fir_bug/project_vitis2020_2/solution1/sim/vhdl/bug_top_exec.vhd:134]
ERROR: [VRFC 10-664] expression has 64 elements ; expected 48 [hls_fir_bug/project_vitis2020_2/solution1/sim/vhdl/bug_top_exec.vhd:137]

It looks like the hlsfir.run() call generates correct VHDL, with the correct ports:

entity bug_top_run is
    generic (
        INPUT_WIDTH  : integer := 24;
        OUTPUT_WIDTH : integer := 48;
        COEF_WIDTH   : integer := 16
    );
    port (
        in_V_dout                      : in  std_logic_vector(INPUT_WIDTH-1 downto 0);
        out_V_din                      : out std_logic_vector(OUTPUT_WIDTH-1 downto 0);
 [etc]

But the calling function (exec(), bug_top_exec.vhd) incorrectly believes the ports look like this:

    component bug_top_run IS
    port (
        in_V_dout : IN STD_LOGIC_VECTOR (7 downto 0);
        out_V_din : OUT STD_LOGIC_VECTOR (63 downto 0);
[etc]

Whereas HLS 2019.1 correctly generates this:

    component run IS
    port (
        in_V_dout : IN STD_LOGIC_VECTOR (23 downto 0);
        out_V_din : OUT STD_LOGIC_VECTOR (47 downto 0);
[etc]

 I've attached code to reproduce. (Default project settings, target part ultrascale+ VU3P). Any help appreciated.

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216 Views
Registered: ‎04-25-2018

Bump?

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