05-17-2019 05:45 AM
I've written a C++ code in Vivado HLS, Run the C simulation, Synthesis, C/RTL simulation valid and I checked the timing diagram, all results are correct.
I used "Export RTL" option, everything works fine and no erros occured. I imported the vhdl project generated by the C/RTL simulation to Vivado 2018. When I run "Combinational Simulation", it stops and show this line in the Testbench.
This is happening for every project that I try to import from HLS.
05-19-2019 07:25 AM
Hi @hamoudyounes ,
Did you come across any error message in Vivado after running simulation? Can you please try exporting an example design from Vivado HLS and check if you are still facing the same issue? Can you please share the Vivado.log and the Vivado_hls.log file to check.
05-19-2019 08:30 AM