Vivado HLS_Warning Message

[thaus_015]

Hi,

I am working with Larger matrix of size 102x204. How to get rid off ?

Code

#define ROWS 102 
#define COLS 204 

..

void SPA_(int matrix[ROWS][COLS], int Gen[ROWS][COLS], int dout[COLS])
{

int i,j,sum=0,k,r2,j2,i2;


int msg[ROWS] = {1,0,1,0,0,0,1,1,1,0,0,0,0,1,1,0,1,0,0,1,0,0,0,0,1,0,0,1,0,1,0,0,0,1,0,1,1,0,0,0,1,0,0,1,0,0,1,0,0,1,0,0,1,0,1,0,1,0,0,0,0,1,0,1,1,0,0,0,1,0,1,1,0,1,0,1,0,1,0,1,0,0,1,0,0,1,0,0,1,0,0,1,0,1,1,0,0,1,1,1,0,0};
int H[ROWS][COLS] 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int count = 0;

Synthesis_Report

Starting C synthesis ...
C:/Xilinx_2015_4/Vivado_HLS/2015.4/bin/vivado_hls.bat E:/Saraswathy/LDPC/NEW_ENCODE_102x204/LDPC_EncoderHls/Encoder_102x204/solution1/csynth.tcl
@I [HLS-10] Running 'C:/Xilinx_2015_4/Vivado_HLS/2015.4/bin/unwrapped/win64.o/vivado_hls.exe'
            for user 'Optics2015A' on host 'optics2015a-pc' (Windows NT_amd64 version 6.1) on Fri Sep 15 16:22:24 +0530 2017
            in directory 'E:/Saraswathy/LDPC/NEW_ENCODE_102x204/LDPC_EncoderHls'
@I [HLS-10] Opening project 'E:/Saraswathy/LDPC/NEW_ENCODE_102x204/LDPC_EncoderHls/Encoder_102x204'.
@I [HLS-10] Adding design file 'Encoder.c' to the project
@I [HLS-10] Opening solution 'E:/Saraswathy/LDPC/NEW_ENCODE_102x204/LDPC_EncoderHls/Encoder_102x204/solution1'.
@I [SYN-201] Setting up clock 'default' with a period of 10ns.
@I [HLS-10] Setting target device to 'xc7k325tffg900-2'
@I [SYN-201] Setting up clock 'default' with a period of 10ns.
@I [HLS-10] Analyzing design file 'Encoder.c' ...
@I [HLS-10] Validating synthesis directives ...
@I [HLS-10] Starting code transformations ...
@I [HLS-10] Checking synthesizability ...
@W [ANALYSIS-31] The program may have out of bound access of array variable 'C' in function 'SPAEncoder' (Encoder.c:118:5).
@W [ANALYSIS-31] The program may have out of bound access of array variable 'C' in function 'SPAEncoder' (Encoder.c:123:2).
@W [XFORM-562] Loop 'Loop-2.1' (Encoder.c:59) in function 'SPAEncoder' has unknown bound because it has multiple exiting blocks.
@I [HLS-111] Elapsed time: 32.514 seconds; current memory usage: 88 MB.
@I [HLS-10] Starting hardware synthesis ...
@I [HLS-10] Synthesizing 'SPAEncoder' ...
@I [HLS-10] ----------------------------------------------------------------
@I [HLS-10] -- Scheduling module 'SPAEncoder'
@I [HLS-10] ----------------------------------------------------------------
@I [SCHED-11] Starting scheduling ...
@I [SCHED-11] Finished scheduling.
@I [HLS-111] Elapsed time: 0.468 seconds; current memory usage: 90.6 MB.
@I [HLS-10] ----------------------------------------------------------------
@I [HLS-10] -- Exploring micro-architecture for module 'SPAEncoder'
@I [HLS-10] ----------------------------------------------------------------
@I [BIND-100] Starting micro-architecture generation ...
@I [BIND-101] Performing variable lifetime analysis.
@I [BIND-101] Exploring resource sharing.
@I [BIND-101] Binding ...
@I [BIND-100] Finished micro-architecture generation.
@I [HLS-111] Elapsed time: 0.437 seconds; current memory usage: 91 MB.
@I [HLS-10] ----------------------------------------------------------------
@I [HLS-10] -- Generating RTL for module 'SPAEncoder'
@I [HLS-10] ----------------------------------------------------------------
@I [RTGEN-500] Setting interface mode on port 'SPAEncoder/sys_matrix' to 's_axilite & ap_memory'.
@I [RTGEN-500] Setting interface mode on port 'SPAEncoder/Generator' to 's_axilite & ap_memory'.
@I [RTGEN-500] Setting interface mode on port 'SPAEncoder/dout' to 's_axilite & ap_memory'.
@I [RTGEN-500] Setting interface mode on function 'SPAEncoder' to 's_axilite & ap_ctrl_hs'.
@W [RTGEN-101] Global array 'SPAEncoder_H' will not be exposed as RTL port.
@I [RTGEN-100] Generating core module 'SPAEncoder_mul_mul_9ns_16s_16_1': 1 instance(s).
@I [RTGEN-100] Finished creating RTL model for 'SPAEncoder'.
@I [HLS-111] Elapsed time: 0.343 seconds; current memory usage: 91.7 MB.
@I [RTMG-279] Implementing memory 'SPAEncoder_SPAEncoder_H_rom' using auto ROMs.
@I [RTMG-279] Implementing memory 'SPAEncoder_msg_rom' using distributed ROMs.
@I [RTMG-278] Implementing memory 'SPAEncoder_C_ram' using distributed RAMs.
@I [RTMG-278] Implementing memory 'SPAEncoder_H_ram' using block RAMs.
@I [RTMG-278] Implementing memory 'SPAEncoder_G_ram' using block RAMs.
@I [HLS-10] Finished generating all RTL models.
@I [WSYSC-301] Generating RTL SystemC for 'SPAEncoder'.
@I [WVHDL-304] Generating RTL VHDL for 'SPAEncoder'.
@I [WVLOG-307] Generating RTL Verilog for 'SPAEncoder'.
@I [HLS-112] Total elapsed time: 36.398 seconds; peak memory usage: 91.7 MB.

[muzaffer · Accepted solution]

@thaus_015 try making it static.

[hpoetzl]

Hey @thaus_015,

How to get rid off?

I presume this refers to the warning messages ...

@W [ANALYSIS-31] The program may have out of bound access of array variable 'C' in function 'SPAEncoder' (Encoder.c:118:5).

Check line 118 in your Encoder.c source file and make sure that the indices used for array C are within the limits of the array.

@W [ANALYSIS-31] The program may have out of bound access of array variable 'C' in function 'SPAEncoder' (Encoder.c:123:2).

Check line 123 in your Encoder.c source file and make sure that the indices used for array C are within the limits of the array.

@W [XFORM-562] Loop 'Loop-2.1' (Encoder.c:59) in function 'SPAEncoder' has unknown bound because it has multiple exiting blocks.

Check line 59 of your Encoder.c source file and make sure that the loop is bound by a maximum loop count.

@W [RTGEN-101] Global array 'SPAEncoder_H' will not be exposed as RTL port.

If you want to expose the global variable H as I/O port, then you have a number of options ...

• Add an external qualifier to the variable.
• Use the INTERFACE directive to specify an I/O protocol.
• Specify the expose_global option with config_interface.

Hope this helps,

Herbert

[thaus_015]

Hi,

Which variable i need to initialize as STATIC?