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656 Views
Registered: ‎07-23-2021

Vivado HLS csim compilation error related to ap_fixed

Hello! When running csim on my project with Vivado HLS 2020.1, I keep getting the following error.

 

INFO: [SIM 2] *************** CSIM start ***************
INFO: [SIM 4] CSIM will launch GCC as the compiler.
   Compiling ../../../../nnet_test.cpp in debug mode
   Compiling ../../../../nnet.cpp in debug mode
csim.mk:75: recipe for target 'obj/nnet.o' failed
make: *** [obj/nnet.o] Error 1
ERR: [SIM 100] 'csim_design' failed: compilation error(s).
INFO: [SIM 3] *************** CSIM finish ***************

 

Unfortunately, the error message is too short to help me locate any issue in my code that may cause this error. Interestingly however, I typedef'ed a data type float24_t in 'headers/defines.h' with code 

typedef ap_fixed<16,4> float24_t

If I change it from ap_fixed to other normal data types like float or double, the error no longer occurs. I wonder what could possibly be the cause of this.

Any help is appreciated! Thanks!

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8 Replies
joancab
Teacher
Teacher
630 Views
Registered: ‎05-11-2015

Don't re-define float. Why rename bananas as 'sausage fruits' if everybody calls them bananas?

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575 Views
Registered: ‎07-23-2021

Sorry if I didn't make it clear in the original post. The problem is not related to renaming the float type. It's just that the error occurs when I use ap_fixed, and is weirdly solved if I use float or double instead.

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joancab
Teacher
Teacher
560 Views
Registered: ‎05-11-2015

Did you just replaced a float type by a fixed point and expected it to work?

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532 Views
Registered: ‎07-23-2021

Actually it’s the other way round. The code was originally using ap_fixed, but didn’t work until we simply changed it to float.

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joancab
Teacher
Teacher
506 Views
Registered: ‎05-11-2015

So, is it that some code borrowed from somewhere? Intended for Vivado HLS? Same release? 

Do you want it to work with fixed?

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randyh
Xilinx Employee
Xilinx Employee
484 Views
Registered: ‎01-04-2013

You could look at line 75 of csim.mk and see what might be causing the failure? You can find it in solution1/csim/build

I was able to get your testcase to go through simulation, and it says it passed even though there were a bunch of empty reads:

WARNING: Hls::stream 'test_FC3_out' is read while empty, which may result in RTL simulation hanging.

Check results
the 0 output is incorrect
the 1 output is incorrect
the 2 output is incorrect
the 3 output is incorrect
the 4 output is incorrect
the 5 output is incorrect
the 6 output is incorrect
the 7 output is incorrect
test 8 passed
all tests passINFO: [SIM 211-1] CSim done with 0 errors.
INFO: [SIM 211-3] *************** CSIM finish ***************
Finished C simulation.

 

436 Views
Registered: ‎07-23-2021

The current code (using float) also runs on my machine. But if I change it to ap_fixed (uncomment the lines in headers/defines.h), it doesn’t work anymore.

randyh
Xilinx Employee
Xilinx Employee
371 Views
Registered: ‎01-04-2013

I got it to run C-sim with ap_fixed:

#include "ap_fixed.h"
#define EXP_WIDTH	16
#define INT_WIDTH	4
//typedef float float24_t;
typedef ap_fixed<EXP_WIDTH,INT_WIDTH> float24_t;

and got the same result as last time. However, it returns errors related to assert when trying to synthesize. 

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