cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
simalps
Observer
Observer
8,511 Views
Registered: ‎06-07-2016

Vivado HLS: dataflow and shared array among modules

Jump to solution

Dear all, I'm trying to synthesize a design using the dataflow pragma and a shared array among modules of the network. As an example, the following Figure summarized the problem.

I have a top network (where I use the dataflow pragma) with two parallel modules: the Writer and the Reader. Basically lets assume that the writer receives the input values through an HLS fifo stream, copy these values in the array, and sends write-done signal to the Reader module  through a second HLS fifo stream. The reader makes some processing on this array and send the output through another  HLS fifo stream. At the same time it sends also a read-done signal to the writer. In other words, both the write-done and the read-done signals emulates a mutex on the array object.

network.png

 

I tried different implementation solutions for the Array object but I can not synthesize this design. Do you have some similar working examples / solutions / suggestions?

Thank you!

Tags (3)
0 Kudos
1 Solution

Accepted Solutions
svanapar
Explorer
Explorer
14,131 Views
Registered: ‎11-25-2015

@simalps

 

What is the error you are getting? How does your code behave when there is no dataflow directive?

Also, dataflow directive has few limitations. Refer Pg:153 http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug902-vivado-high-level-synthesis.pdf. Make sure your code doesn't fall into these categories.

 

Thanks,

Sravanthi

View solution in original post

0 Kudos
6 Replies
svanapar
Explorer
Explorer
14,132 Views
Registered: ‎11-25-2015

@simalps

 

What is the error you are getting? How does your code behave when there is no dataflow directive?

Also, dataflow directive has few limitations. Refer Pg:153 http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug902-vivado-high-level-synthesis.pdf. Make sure your code doesn't fall into these categories.

 

Thanks,

Sravanthi

View solution in original post

0 Kudos
simalps
Observer
Observer
8,455 Views
Registered: ‎06-07-2016

@svanapar thank your for your reply

Now my design can be synthesized, but I still have wrong co-simulation results. I attached the source code with this implementation at the end of this message.

The co-symulation give me wrong results. The test bench works like this: I send to the network 64*4 tokens through the input fifo with value [0,..., 64*4-1]. The reader store 64 tokens on the array, then send a write-done to the  reader and waits a read-done signal before reading and storing the new 64 tokens. The output values of the network should be basically the same input values, since I send each time the 64 values contained in the array. The co-symulation errors ate basically two: (see Figure below)

  1. The output values are always 0s
  2. The writer does not wait for the read-done signal and seams that it continues working

result.png

Without the DATAFLOW it works. According to ug902  the coding styles prevent Vivado HLS from performing the DATAFLOW optimization are:

  • Single-producer-consumer violations
  • Bypassing tasks
  • Feedback between tasks -> could be this one the problem?
  • Conditional execution of tasks
  • Loop scopes with variable bounds
  • Loops with multiple exit conditions

So a second attempt has been to introduce two internal buffers to decouple the direct feedback loop between the Writer and the Reader (i.e. through the read-done and write-done fifos). Results depends on the buffer depth. With  depth 1 I have the same results as previously, with depth 512 results are correct only for the first 64 tokens, then the simulation stacks (see Figure below) with the following error:

////////////////////////////////////////////////////////////////////////////////////
// Inter-Transaction Progress: Completed Transaction / Total Transaction
// Intra-Transaction Progress: Measured Latency / Latency Estimation * 100%
////////////////////////////////////////////////////////////////////////////////////
// RTL Simulation : 0 / 530 [0.00%] @ "125000"
// RTL Simulation : 530 / 530 [0.00%] @ "5435000"
////////////////////////////////////////////////////////////////////////////////////
$finish called at time : 5475 ns : File "/home/user/hls_test_forum/projects/SharedNetwork/hls_SharedNetwork/SharedNetwork_solution/sim/verilog/SharedNetwork.autotb.v" Line 270
## quit
INFO: [Common 17-206] Exiting xsim at Sun Aug 21 12:25:51 2016...
INFO: [COSIM 212-316] Starting C post checking ...
CRITICAL WARNING: [COSIM 212-361] C TB post check failed, nonzero return value '1'.
CRITICAL WARNING: [COSIM 212-4] *** C/RTL co-simulation finished: FAIL ***
command 'ap_source' returned error code
    while executing
"source /home/user/hls_test_forum/projects/SharedNetwork/hls_SharedNetwork/SharedNetwork_solution/cosim.tcl"
    invoked from within
"hls::main /home/user/hls_test_forum/projects/SharedNetwork/hls_SharedNetwork/SharedNetwork_solution/cosim.tcl"
    ("uplevel" body line 1)
    invoked from within
"uplevel 1 hls::main {*}$args"
    (procedure "hls_proc" line 5)
    invoked from within
"hls_proc $argv"
Finished C/RTL cosimulation.

 ex2.png

 

I think that one problem can be also the synchronization between the two modules and seems that the Writer is not blocked when waiting the read-done signal from the Reader.


Do you have any idea?

Once again, thank you for assistance

0 Kudos
rabeluk
Visitor
Visitor
7,923 Views
Registered: ‎06-09-2016

Hi all,

 

I've the same problem. Can someone help me  please?

0 Kudos
simalps
Observer
Observer
7,896 Views
Registered: ‎06-07-2016

Unfortunately you can not do that.

You have to make an IP core for each network module and successively connect them using Vivado.

In this way it works.

0 Kudos
rabeluk
Visitor
Visitor
7,887 Views
Registered: ‎06-09-2016

Hi simalps,

Thanks for answer

How do you bring out from module the array? I need to bring out an array of struct

0 Kudos
simalps
Observer
Observer
7,877 Views
Registered: ‎06-07-2016

@rabeluk my solution is: I defined a pointer in the module input parameters. I used the AXI master as interface. Then I control/assign the pointer address through the PS.

0 Kudos