When I use array in SystemC, a problem was happened.
If I use array in SC_MODULE, Vivado HLS 2019.2 generates syntax error-Verilog codes.
In SystemC, as follows,
and in generated Verilog, as follows, waste "end" is the error
Arrays are not surported in SystemC?
Please tell me how to use array with no syntax error-Verilog code.