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Registered: ‎06-09-2020

Vivado & Vitis: Cannot write to memory. UG871 Chap10, Lab1

Dear All,

I have been struggling with this problem for days. My environment is WIN10, Vivado Design Suit 2019.2

I am following the ug871-vivado-high-level-synthesis-tutorial Chapter10 Lab 1 which is a simple AXI slave IP, trying to use the PS to talk to the AXI slave. The only difference is I am using zcu102 board. The problem is that, in the Vitis (SDK), when I put input parameters to the slave ip's address, this function


Xil_Out32(Addr, Value)  #put a 32bit data into address


 is called, and the program will jump to line 206: b _boot in the asm_vectors.S and freeze. 

I am sure that I put the correct slave address on it. Here is the design and the salve address segmentation:



From the picture above, the "Data" starts from 0xA0000000. The hls slave starts from 0xA0000000 and ends at 0xA000FFFF

I am not able to read from or write to any memory location above 0xA0000000. In the debug mode's memory monitor, even if I try to see memory location>0xa0000000, the program will still jump to b _boot in the asm_vectors.S and freeze.

read or write an address below offset address, like 0x9000000 is successful. Once the address is >= 0xa0000000, there will be a problem.

 Any help or reply is super appreciated!!



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2 Replies
Registered: ‎08-02-2019

Hi  @xjcwd1101 ,

I'm using ZC702 as your reference document. I have never used Ultrascale before, but I am experienced about AXI Slave and Masters interfaces.

I can refer you about two suspicious parts:

  1. Wrong mapped address on Vivado.
  2. SDK & Vivado sync. issue.

1. Suspicious:

When I add this kind of custom Ip Core to Block design, Vivado gives an address automatically to this Ip Core. I have never changed it and it is seems always 0x43C00000, when I add a similar Ip core, it take an address like that: 0x43C10000.

I'm not sure, but I think your problem is because of that address. I can recommend you:

  • On address editor window, unmap your ip core, let it to give an address automaticall by clicking "Map unmapped Ip Cores/Auto Assign Address". 
  • Remove output Products
  • Generate output Products
  • Validate Design
  • Generate bitstream

Second Suspicious:

Always we need to be sure, our bit stream/ hdf file really sync. with our SDK.

Sometimes Vivado and SDK lost sync. and you can see under your project list more than one 

"design_1_wrapper_hw_platform_0" , "design_1_wrapper_hw_platform_1"...

Than even if you export your hdf to SDK, Bare Metal project can lose sync. with your new bit stream/hdf file.

To solve that problem, I'm running most of the time Re-generate BSP sources on SDK to make it sync.

If it does not work, I'm removing bsp project from my work space and re-create it again(it takes less time than to try to solve problem.)

Finally, I can say:

Instead of using manually typed addresses we should use alliases from "xparameters.h" or "xparameters_ps.h".

If SDK and Vivado properly sync. to each other, it gives always correct addresses to us.


/* Definitions for peripheral CUSTOM_IP_CORE_1 */
#define CUSTOM_IP_CORE_1_BASEADDR 0x43C10000




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Registered: ‎06-09-2020

Hi @sabankocal ,


Thank you so much for your reply. I paid attention to the procedures and configurations and it still didn't work.

I think the problem is that I am using Vivado 2019.2 version. My co-worker is using Vivado 2020 version and it can run well and see the memory map. I am downloading the 2020.1 Version now.




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