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30,900 Views
Registered: ‎02-11-2013

Vivado: create a simple AXI4-Master IP core

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Hi,

 

I'm new to Vivado HLS and I want to create a simple peripheral that is able to write some data through AXI4-burst write operations. The data and address can be statically defined, since, for now,  the core will emulate an acquisition device, continuously writing to some memory area.

 

I want to use this tool mainly because I believe that it will significantly reduce the development time, by avoiding the need for me to understand the AXI4 bus signal details. 

 

Can anyone provide me some ref. designs, examples or tutorials that would help me to create such a simple core?

 

Thank you.

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43,720 Views
Registered: ‎02-11-2013

Re: Vivado: create a simple AXI4-Master IP core

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As a matter of fact, the change I've made in the previous post works and it gives me control of the AXI-Master Transfer through an AXI-Slave Lite accessible register.

 

The tweak was to "Acknowledge" the value of C_o after a transfer was completed before starting a new one.

 

I've attached the source file I've used to test it successfully using SDK to program the Zynq on a Zedboard, plus the final Vivado HLS source file.

View solution in original post

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11 Replies
30,889 Views
Registered: ‎02-11-2013

Re: Vivado: create a simple AXI4-Master IP core

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I've managed to find some pointers on the vivado-hls userguide:

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_3/ug871-vivado-high-level-synthesis-tutorial.pdf

 

However, I'm trying to understand how can I control the AXI4-Master example to perform the read/write operations.

I've tried to create an AXI-slave control register to start the master transaction by modifying the code example of the user guide for the AXI-master:

 

void foo_top (DT* c, volatile DT *m) {

// Define the RTL interfaces
#pragma HLS interface ap_ctrl_none port=return
#pragma HLS interface ap_bus port=m

#pragma HLS interface ap_none port=c
// Define the pcore interface as an AXI4 master
#pragma HLS resource core=AXI4M variable=m

#pragma HLS resource core=AXI4LiteS variable=c

 

DT buff[N], tmp;
int i, j;

if(*c==1)
{
memcpy(buff, m, N * sizeof(DT));

loop:for (i = 0, j = N - 1; i < j; i++, j--) {
tmp = buff[i];
buff[i] = buff[j];
buff[j] = tmp;
}

memcpy(m, buff, N * sizeof(DT));
}
*c = 0;
}

 

After exporting the RTL as a pcore to EDK, it doesn't seem to work at all.

One of the problems might be that the register "c" is actually split into two registers, is there anyway to avoid this?

I want to assert it to '1' to start the transaction, using the axi interface, and then I want it to automatically deassert.

Is there any other way to accomplish this ? I basically need to understand how to control the AXI-master transactions.

 

 

 

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43,721 Views
Registered: ‎02-11-2013

Re: Vivado: create a simple AXI4-Master IP core

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As a matter of fact, the change I've made in the previous post works and it gives me control of the AXI-Master Transfer through an AXI-Slave Lite accessible register.

 

The tweak was to "Acknowledge" the value of C_o after a transfer was completed before starting a new one.

 

I've attached the source file I've used to test it successfully using SDK to program the Zynq on a Zedboard, plus the final Vivado HLS source file.

View solution in original post

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Explorer
Explorer
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Registered: ‎12-01-2010

Re: Vivado: create a simple AXI4-Master IP core

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ah!  this is exactly what i've been trying to do, without success.  could you please post the pcore HDL of your simple AXI4 Master ?

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Explorer
Explorer
30,839 Views
Registered: ‎12-01-2010

Re: Vivado: create a simple AXI4-Master IP core

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I'm pretty new to C/++, and since i couldn't make heads or tails out of your HDL, i wrote a simple function to test out the instantiated code.  It does a burst DMA WRITE from the IP to the AXI slave memory only.

  No reads (see:  Forum Post : Bus2IP_mst_cmplt signal never raises).

 

  I hope some find it helpful:

 

#include "platform_config.h"
#include "AXI_MASTER_WRITER.h"

extern void write_DDR3_values(Xuint32,int);
extern void print_DDR3_values(Xuint32,int);


void Master_writer()
{
	Xuint32 BASEADDR = 0x30000000;	// base address of IP
	Xuint32 OFFSET = 0x100;	// offset for master register

	Xuint32 DDR_ADDR = 0x90000000;	// Target location of the DMA, space inside the DDR3 memory
	int read_rows = 8;	// each row is 4 sets of four bytes, for 16 bytes total

	int write_rows = 7;  // 255 MAX.  AXI4 limits bursts to 4096 bytes


	print("Initial DDR3 Memory values:\r\n");	// initialize the DDR with some known value
	write_DDR3_values(DDR_ADDR,read_rows);
	print_DDR3_values(DDR_ADDR,read_rows);

	print("Do a master write to AXI\n\r");

        AXI_MASTER_WRITER_mWriteSlaveReg0(BASEADDR,OFFSET,0xA);	// write with burst support
        AXI_MASTER_WRITER_mWriteSlaveReg1(BASEADDR,OFFSET,DDR_ADDR);	// target location
        AXI_MASTER_WRITER_mWriteSlaveReg2(BASEADDR,OFFSET,0xFFFF);	// all bytes are enabled
//     AXI_MASTER_WRITER_mWriteSlaveReg3(BASEADDR,OFFSET,0xA);  (redundant)
        xil_printf("\t REG 0: 0x%X\r\n",AXI_MASTER_WRITER_mReadSlaveReg0(BASEADDR,OFFSET));
 	xil_printf("\t REG 1: 0x%X\r\n",AXI_MASTER_WRITER_mReadSlaveReg1(BASEADDR,OFFSET));
 	xil_printf("\t REG 2: 0x%X\r\n",AXI_MASTER_WRITER_mReadSlaveReg2(BASEADDR,OFFSET));
// 	xil_printf("\t REG 3: 0x%X\r\n",AXI_MASTER_WRITER_mReadSlaveReg3(BASEADDR,OFFSET));


 	print("execute GO register\r\n");
        AXI_MASTER_WRITER_mWriteSlaveReg3(BASEADDR,OFFSET,0x0a000000 + (0x10 * write_rows));  // go command with the number of bytes to write

        xil_printf("\t REG 0: 0x%X\r\n",AXI_MASTER_WRITER_mReadSlaveReg0(BASEADDR,OFFSET));	// read the status/command register
        AXI_MASTER_WRITER_mWriteSlaveReg0(BASEADDR,OFFSET,0x0);	// clear the master register 0 (command & status)
        xil_printf("\t REG 0: 0x%X   (after reset)\r\n",AXI_MASTER_WRITER_mReadSlaveReg0(BASEADDR,OFFSET));	// read the status/command register again
//	if this value is non-zero, then the user_logic state machine got stuck, most likely on a  "busy" command due to a missed BUS2IP_mst_cmplt signal

	print("Final DDR3 Memory values:\r\n");		// This should have changed!  If it didn't, the DMA FAILED.
	print_DDR3_values(DDR_ADDR,read_rows);
}


void write_DDR3_values(Xuint32 DDR_ADDR, volatile int loop_cnt){
	volatile int i;

	for (i=0;i<loop_cnt;i++){
		WR_WORD(DDR_ADDR + 0xC + (i*16), 0xdeadbbbf);
		WR_WORD(DDR_ADDR + 0x8 + (i*16), 0xdeadbccf);
		WR_WORD(DDR_ADDR + 0x4 + (i*16), 0xdeadbddf);
		WR_WORD(DDR_ADDR + (i*16), 0xdeadbeef);
	}
}


void print_DDR3_values(Xuint32 DDR_ADDR, volatile int loop_cnt){
 	volatile Xuint32 DDR_data;
	volatile int i;

	for (i=0;i<loop_cnt;i++){
		RD_WORD(DDR_ADDR + 0xC + (i*16), DDR_data);
	 	xil_printf(" DDR @ 0x%X %X",(DDR_ADDR + (i*0x10)),DDR_data);
		RD_WORD(DDR_ADDR + 0x8 + (i*16), DDR_data);
	 	xil_printf(" %X",DDR_data);
		RD_WORD(DDR_ADDR + 0x4 + (i*16), DDR_data);
	 	xil_printf(" %X",DDR_data);
		RD_WORD(DDR_ADDR + (i*16), DDR_data);
	 	xil_printf(" %X\n\r",DDR_data);
	}
}

 

This codes uses the drivers & IP generated by instantiating an AXI master IP (named AXI_MASTER_WRITER) within XPS (14.4) via Hardware -> Create or Import Peripheral.

 


The results look like this:


Initial DDR3 Memory values:
 DDR @ 0x90000000 DEADBBBF DEADBCCF DEADBDDF DEADBEEF
 DDR @ 0x90000010 DEADBBBF DEADBCCF DEADBDDF DEADBEEF
 DDR @ 0x90000020 DEADBBBF DEADBCCF DEADBDDF DEADBEEF
 DDR @ 0x90000030 DEADBBBF DEADBCCF DEADBDDF DEADBEEF
 DDR @ 0x90000040 DEADBBBF DEADBCCF DEADBDDF DEADBEEF
 DDR @ 0x90000050 DEADBBBF DEADBCCF DEADBDDF DEADBEEF
 DDR @ 0x90000060 DEADBBBF DEADBCCF DEADBDDF DEADBEEF
 DDR @ 0x90000070 DEADBBBF DEADBCCF DEADBDDF DEADBEEF
Do a master write to AXI
     REG 0: 0xA
     REG 1: 0x90000000
     REG 2: 0xFFFF
execute GO register
     REG 0: 0x50A
     REG 0: 0x0   (after reset)
Final DDR3 Memory values:
 DDR @ 0x90000000 1234C0CA 5678C01A 1234C0CA 5678C01A
 DDR @ 0x90000010 1234C0CA 5678C01A 1234C0CA 5678C01A
 DDR @ 0x90000020 1234C0CA 5678C01A 1234C0CA 5678C01A
 DDR @ 0x90000030 1234C0CA 5678C01A 1234C0CA 5678C01A
 DDR @ 0x90000040 1234C0CA 5678C01A 1234C0CA 5678C01A
 DDR @ 0x90000050 1234C0CA 5678C01A 1234C0CA 5678C01A
 DDR @ 0x90000060 1234C0CA 5678C01A 1234C0CA 5678C01A
 DDR @ 0x90000070 DEADBBBF DEADBCCF DEADBDDF DEADBEEF


 

If you did not edit the User_logic.vhd file, then your final memory vales will be Zeroes, as the FIFO inside the IP is empty. 

 

For the output above, I made a simple edit at the bottom of the VHDL file to always write the same 64bit value to the AXI slave:

 

 

  DATA_CAPTURE_FIFO_I : entity proc_common_v3_00_a.srl_fifo_f
    generic map
    (
      C_DWIDTH   => C_MST_NATIVE_DATA_WIDTH,
      C_DEPTH    => 128
    )
    port map
    (
      Clk        => Bus2IP_Clk,
      Reset      => Bus2IP_Reset,
      FIFO_Write => mst_fifo_valid_write_xfer,
      Data_In    => Bus2IP_MstRd_d,
      FIFO_Read  => mst_fifo_valid_read_xfer,
      Data_Out   => open,--IP2Bus_MstWr_d,    -- changed to open (MPZ 3/6/2013)
      FIFO_Full  => open,
      FIFO_Empty => open,
      Addr       => open
    );
	 
	IP2Bus_MstWr_d <= x"1234c0ca5678c01a";  -- added (MPZ 3/6/2013)
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30,813 Views
Registered: ‎02-11-2013

Re: Vivado: create a simple AXI4-Master IP core

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That works fine, the problem was using Vivado HLS to create a similar peripheral, but I guess you don't need that in your case right?
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Newbie elody
Newbie
26,390 Views
Registered: ‎07-10-2014

Re: Vivado: create a simple AXI_LITE-Master IP core and AXI_LITE-slave IP

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Hi,
I want create two IP ( master and slave) and i want send a data from master to slave , by using axi bus.
i want programme on C. Same one have one exemple for this ?I want work on the Zynq zeadbord 7zc702.
SAme one can help me please.
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Xilinx Employee
Xilinx Employee
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Registered: ‎11-28-2007

Re: Vivado: create a simple AXI_LITE-Master IP core and AXI_LITE-slave IP

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Can you explain why these two IPs need to communicate directly with ap_bus instead of one IP writes to a memory and the other IP reads from the same memory?

 


@elody wrote:
Hi,
I want create two IP ( master and slave) and i want send a data from master to slave , by using axi bus.
i want programme on C. Same one have one exemple for this ?I want work on the Zynq zeadbord 7zc702.
SAme one can help me please.



Cheers,
Jim
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25,669 Views
Registered: ‎02-15-2014

Re: Vivado: create a simple AXI4-Master IP core

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Hi,

I need to implement a AXI Master in HLS to take data from the DDR memory, process and write back to DDR. I'm using a Zedboard and Vivado 2014.2. I tried the code above but it doesn't work and I can't understand why. Everybody here seems could you it without problem.

 

I explain what i did:

1) I crete a new project in HLS and copy and paste the code. I had to replace the line

#pragma HLS resource core=AXI4LiteS port=c

with

#pragma HLS resource core=AXI4LiteS variable=c

2) I compiled and exported the code as ip core

3) I create a new project in VIVADO with the zynq. I configured the zynq with the standard preset for the Zedboard and i enabled an axi master and a GP axi slave. I added two axi inteconnect blocks and the AMV block generated in HLS.

4) I changed the base address inside the properties of the AMV block from 0x00000000 to 0x1bb00000.

5) I press the button to assign the addresses and i got 0x0 for the slave (zynq side) port and 0x43c00000 for the master.

7) Compile export the project and open the sdk.

8) add the drivers to a new hello word project

9) copy and paste che code in SDK. there's an error and i could understand in witch way the code in main.c could work.... int ptr=.... is not a pointer. I replaced with int *ptr; ptr=....

10) program and run

 

 

when c is set to 1 it correctly goes back to 0 but no master transaction appens. i check with the chipscope and there is no activity on the AXI master bus.

 

someone has some idea?

is there some one that has a working axi master code? please, could you send me?

 

Thanks

 

Andrea 

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Newbie mletras
Newbie
21,143 Views
Registered: ‎04-26-2015

Re: Vivado: create a simple AXI4-Master IP core

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Hi Andrea

 

I'm having the same mistake, if you have fixed it, can you explain me where is the error?

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Contributor
Contributor
6,767 Views
Registered: ‎05-27-2015

Re: Vivado: create a simple AXI4-Master IP core

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Hi, 

 

In your application in SDK, before performing HW acceleration , have you disabled the cache ? 

 

If not, you can do this by using the following function :

 

#include "xil_cache.h" 
Xil_DCacheDisable();

 

Kind Regards,

Abdul

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Observer bulunhaimu
Observer
3,089 Views
Registered: ‎11-21-2016

Re: Vivado: create a simple AXI4-Master IP core

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Hi, Thank you for your code. I have a question about your design that is how could you get to know the memory address?

#define XPS_DEFINED_MEM_ADDRESS 0x1bb00000

Why do you set the address like this? The IP generated by HLS does not know where to send this value.

Thank you very much

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