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Observer
Observer
7,314 Views
Registered: ‎11-13-2012

VivadoHLS Co-simulation Error

Hi everyone,

 

I am new to Vivado HLS. When I want to perform a C/RTL co-simulation with SystemC I get the following error:

 

---------------------------------------------------------------------------------------------------- 

In memory model top.AESL_inst_dstGrid.core_inst, during a write cycle
ERROR: Address 32570 for port '1' is outside the legal range [0..25999].

Fatal: (F1000) unknown id
In file: AESL_automem_dstGrid.h:102
In process: top.AESL_inst_dstGrid.core_inst.proc_mem @ 105 ns
@E [SIM-304] Aborting co-simulation: C simulation failed.
@E [SIM-4] *** C/RTL co-simulation finished: FAIL ***

----------------------------------------------------------------------------------------------------

 

Had anyone encountered something similar? How could I fix this issue?

I would appreciate any help.

 

Thank you,

Alex

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6 Replies
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Explorer
Explorer
7,307 Views
Registered: ‎09-06-2012

Hi,

 

which version of VHLS are you using??

 

Ankury

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Observer
Observer
7,303 Views
Registered: ‎11-13-2012

Hi Ankury,

 

it's 2012.2.1

 

Alex

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Highlighted
Observer
Observer
7,301 Views
Registered: ‎11-13-2012

... and I synthesise it for Zynq xc7z020clg484-1
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Highlighted
Observer
Observer
7,297 Views
Registered: ‎11-13-2012

I also tried to simulate a much simpler design, top function is "array_axi_m". Running the program in C works fine, as well as the synthesis, but not the C/RTL co-simulation

--------------------------------------------------------------------------

void doit(
        volatile float *src_addr,
        volatile float *dst_addr) {
    int i;
    for (i = 0; i < SIZE; i++) {
        dst_addr[i] = src_addr[i] * 10.0 + 11.0;
    }
}

void array_axi_m(
        volatile float *bus,
        volatile uintptr_t *p_srcGrid,
        volatile uintptr_t *p_dstGrid) {


    doit((float *)(bus + *p_srcGrid / 4), (float*)(bus + *p_dstGrid / 4));
}

--------------------------------------------------------------------------

With the following directives:

set_directive_interface -mode ap_bus "array_axi_m" bus
set_directive_resource -core AXI4M "array_axi_m" bus
set_directive_interface -mode ap_none "array_axi_m" p_srcGrid
set_directive_resource -core AXI4LiteS "array_axi_m" p_srcGrid
set_directive_interface -mode ap_none "array_axi_m" p_dstGrid
set_directive_resource -core AXI4LiteS "array_axi_m" p_dstGrid

 

And the testbench:

--------------------------------------------------------------------------

int main(int argc, char* argv[]) {
    float *in;
    float *out;
    float **in_p;
    float **out_p;
    int i;

    in = (float*)malloc(SIZE * sizeof(float));
    out = (float*)malloc(SIZE * sizeof(float));
    in_p = &in;
    out_p = &out;

    for (i = 0; i < SIZE; i++) {
        in[i] = (float)i;
    }

    array_axi_m(NULL, (uintptr_t*)in_p, (uintptr_t*)out_p);

    for (i = 0; i < SIZE; i++) {
        if (out[i] != in[i] * 10. + 11.) {
            return -1;
        }
    }
    return 0;
}

--------------------------------------------------------------------------

 

And I get the error:

@I [SIM-302] Generating test vectors ...
@E [SIM-304] Aborting co-simulation: C simulation failed.
@E [SIM-320] Generating test vectors failed.
@E [SIM-4] *** C/RTL co-simulation finished: FAIL ***

 

Could please someone help me with this?

 

Regards,

Alex

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Highlighted
Visitor
Visitor
6,761 Views
Registered: ‎09-07-2013

Hi, 

Did you resolve your problem?

I have the same problem when runing the cosimulation.

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Xilinx Employee
Xilinx Employee
6,728 Views
Registered: ‎08-17-2011

Hello,

Please start a new thread explaining what you see and attach a testcase, to make it easier to reproduce.

The thread you're replying is too old, and there are a few issues in the code (!).

The OP was also using a year old tool version which may have other issues than the current version.

Thanks.

- Hervé

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