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atikah_daud
Participant
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Registered: ‎03-23-2016

Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.

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Hello,

 

I'm using Vivado HLS 2014.1.

My C++ code run smoothly in simulation and synthesis. But, while running C/RTL cosimulation, i get this warning:

 

Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0.

 

Can I know, this warning is due to what?

 

What do U,X,W,Z represent to?

 

In my C++ code, i do math calculation in floating-point.

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eilert
Teacher
Teacher
7,207 Views
Registered: ‎08-14-2007

Hi,

these values come from the simulators extended set of logic values.

You find a description if you are looking for the definition of VHDL std_logic types.

In brief:

'U' -  Unassigned

'X' - Unknown

'W' - Weak

'Z' - High Impedance

'-' - Don't Care

 

As muzaffer already explained, this mostly appears if there are missing initialisations at the beginning of a simulation.

But there may also be other causes.

What happens in the simulation when the warning appears?

Look at the waveform of the affected signal(s) at the time of the warning and short before (even at delta cycle level). The simulator should show you which value is in the wrong state.

 

Have a nice simulation

   Eilert

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muzaffer
Teacher
Teacher
4,447 Views
Registered: ‎03-31-2012

@atikah_daud this means that there are some uninitialized, uknown, weak or unconnected (respectively) signals in the design. This could happen before a reset is applied. If this warning happens only during the early stages of the simulation and if your cosim passes then you are most probably OK. 

- Please mark the Answer as "Accept as solution" if information provided is helpful.
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atikah_daud
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Registered: ‎03-23-2016

@muzaffer, i have assigned the initialized value for each variable involve in my calculation.

 

Is it possible the cause of the problem due to pass by address in the code?

 

What does U,X,W,Z represent?

 

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eilert
Teacher
Teacher
7,208 Views
Registered: ‎08-14-2007

Hi,

these values come from the simulators extended set of logic values.

You find a description if you are looking for the definition of VHDL std_logic types.

In brief:

'U' -  Unassigned

'X' - Unknown

'W' - Weak

'Z' - High Impedance

'-' - Don't Care

 

As muzaffer already explained, this mostly appears if there are missing initialisations at the beginning of a simulation.

But there may also be other causes.

What happens in the simulation when the warning appears?

Look at the waveform of the affected signal(s) at the time of the warning and short before (even at delta cycle level). The simulator should show you which value is in the wrong state.

 

Have a nice simulation

   Eilert

View solution in original post

atikah_daud
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Participant
4,396 Views
Registered: ‎03-23-2016

Thank you so much mr. @eilert and mr. @muzaffer. It clarify my doubt.

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atikah_daud
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4,395 Views
Registered: ‎03-23-2016
I didn't see that you already mention what is represent by U,X,W and Z. Thank mr. muzaffer.
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