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milan_mian
Explorer
Explorer
7,890 Views
Registered: ‎11-21-2014

Why clock frequency different after HLS in IP?

Hi. I am wondering why the clock frequency got different after HLS in IP.

You can see that Target clock period is 10 ns.

 

 1.png

 

 

After C synthesis, following is report.

 

2.png

After IP integrator in Vivado, I did synthesis but get error.

 

[BD 41-237] Bus Interface property FREQ_HZ does not match between /fmc_imageon_vita_color/Mod_CFA_Interpolation_0/S_AXI_CTRL(142857132) and /processing_system7_0_axi_periph/xbar/M03_AXI(50000000)

 

So, I edited the IP in IP Packager to check and see what is the clock period of the IP.

 

In one of verilog file(just below top verilog file), I find this info.

(* CORE_GENERATION_INFO="Mod_CFA_Interpolation,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.650000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=1,HLS_SYN_DSP=0,HLS_SYN_FF=239,HLS_SYN_LUT=529}" *)

 

I can see the HLS input clock is 10 ns, but there is another sync clock which is 7.65 ns( I don't know what this means).

Upon doing the mathematics, 7.65 ns is 130.718 MHz.

 

I am wondering where is the problem and also what is the meaning of target clock frequency as set in the HLS and frequency after HLS in IP?

 

Please help.

 

 

 

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debrajr
Moderator
Moderator
7,848 Views
Registered: ‎04-17-2011

Try to do an Evaluate option in Export RTL. It would tell you a better Timing score.
Regards,
Debraj
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