UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer chang.y.ab
Observer
7,316 Views
Registered: ‎02-26-2014

Why the HLS generates 2 port output interface?

Dear All:

 

I have a problem that the HLS generates 2 port output memory interface automaticlly.

Because the memory cannot be writen by 2 ports simultaneously,

I should prepare 2 memories for the ports and combine the data.

It is a strange process. How to avoid the 2 port memory output?

 

Best regards,

 

Yuyuan CHANG

0 Kudos
2 Replies
Highlighted
Xilinx Employee
Xilinx Employee
7,314 Views
Registered: ‎08-17-2011

Re: Why the HLS generates 2 port output interface?

hello @chang.y.ab 

 

you can check the resource directive - use either pragma or tcl command but looks like you want to always do this so C pragma may be better.

 

***UG920 Chapter 4: High-Level Synthesis Reference Guide***

To specify which memory element in the library to use to implement an array, use the

set_directive_resource command. For example, this allows you to control whether

the array is implemented as a single or a dual-port RAM. This usage is important for arrays

on the top-level function interface, because the memory associated with the array

determines the ports in the RTL.

***

 

I HTH

 

- Hervé

SIGNATURE:
* New Dedicated Vivado HLS forums* http://forums.xilinx.com/t5/High-Level-Synthesis-HLS/bd-p/hls
* Readme/Guidance* http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

* Please mark the Answer as "Accept as solution" if information provided is helpful.
* Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos
Teacher muzaffer
Teacher
7,278 Views
Registered: ‎03-31-2012

Re: Why the HLS generates 2 port output interface?

Maybe you don't have to avoid 2 port memory? Xilinx FPGAs have what's called "true dual-port memory" feature where you have two completely separate ports through which you can do independent reads and writes, ie it's certainly possible to read from two different addresses at once.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos