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Visitor gilg
Visitor
2,375 Views
Registered: ‎12-29-2016

XC7K480T

I've synthesized c-code using Vivado-HLS 2016.4 and XC7K480T FPGA.

According to HLS report, there are 597,200 LUT's available.

However, when synthesizing the Verilog output code using Vivado 2016.4 and the same FPGA,

the tool fails due to lack of LUT's resource - only 298,600 are available.

This number meets Xilinx datasheet - 74,650 slices with 4 LUT's per slice.

I would like to understand the difference between Vivado-HLS and Vivado LUT resources usage.

 

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1 Reply
Moderator
Moderator
2,198 Views
Registered: ‎04-17-2011

Re: XC7K480T

Try running Export RTL with Evaluate Option to see the LUT count in HLS tool but this looks to be an error in the reporting at HLS as ideally the exact count is known in Vivado Synth & Impl.
Regards,
Debraj
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