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alexafi
Observer
Observer
4,825 Views
Registered: ‎11-13-2012

ap_bus verification failure

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Hi everyone,

 

I have difficulties verifying my design using C co-simulation. Did anyone succeed in verifying an "ap_bus" interface?

 

This is my top function:

void axi_master_example(volatile int *a){
//    a[0] = 4; //works

//    a[20] = 4; //doesn't work
    a[20] = a[10] + 4; //doesn't work
}

 

This is the directives.tcl :

set_directive_interface -mode ap_ctrl_hs -register "axi_master_example"
set_directive_resource -core AXI4LiteS "axi_master_example" return
set_directive_interface -mode ap_bus -depth 300 "axi_master_example" a
set_directive_resource -core AXI4M "axi_master_example" a

 

This is the testbench:

int main() {
    int a[100];
    int i;
    for (i = 0; i < 50; i++) {
        a[i] = i;
    }

    axi_master_example(a);
    return 0;
}

 

And this is the error message:

SystemC: simulation stopped by user.
@I [SIM-316] Starting C post checking ...
@E [SIM-304] Aborting co-simulation: C simulation failed.
@E [SIM-4] *** C/RTL co-simulation finished: FAIL ***
@I [LIC-101] Checked in feature [HLS]

 

I would appreciate any hints.

Thank you,

Alex

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herver
Xilinx Employee
Xilinx Employee
5,797 Views
Registered: ‎08-17-2011
Hi Alex,

I haven't had a deep thought about this yet nor tried myself.
However you should set the depth matching in the directive and the C TB or alternatively no depth in the directives;

what I mean is that something different doesn't look helpfull: if you think about it, the HW/RTL *may* have been generated with something that has depth 300 but you're connecting a buffer with only 100 elements...

I hope this makes some kind of sense..
- Hervé

SIGNATURE:
* Vivado HLS forums* http://forums.xilinx.com/t5/High-Level-Synthesis-HLS/bd-p/hls
* Readme/Guidance* http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

* Please mark the Answer as "Accept as solution" if information provided is helpful.
* Give Kudos to a post which you think is helpful and reply oriented.

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2 Replies
herver
Xilinx Employee
Xilinx Employee
5,798 Views
Registered: ‎08-17-2011
Hi Alex,

I haven't had a deep thought about this yet nor tried myself.
However you should set the depth matching in the directive and the C TB or alternatively no depth in the directives;

what I mean is that something different doesn't look helpfull: if you think about it, the HW/RTL *may* have been generated with something that has depth 300 but you're connecting a buffer with only 100 elements...

I hope this makes some kind of sense..
- Hervé

SIGNATURE:
* Vivado HLS forums* http://forums.xilinx.com/t5/High-Level-Synthesis-HLS/bd-p/hls
* Readme/Guidance* http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

* Please mark the Answer as "Accept as solution" if information provided is helpful.
* Give Kudos to a post which you think is helpful and reply oriented.

View solution in original post

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alexafi
Observer
Observer
4,815 Views
Registered: ‎11-13-2012

Hi Herve,

 

thanks a lot for the help, you were right. Changing to depth 100 or removing it completely (which default to depth=1) solved the issue.

 

However, in Vivado HLS User Guide UG902 p.63, it says that

"When multi-access pointers are used at the interface, High-Level Synthesis must be
informed of the maximum number of reads or writes on the interface. When specifying the
interface, use the depth option on the INTERFACE directive as shown in Figure 2-33."

The above statement contradicts with your solution. What is the right aproach in setting the depth option?

 

The tool doesn't give any clue why the simulation failed. Is there a finer log setting or something to get the cause of the error? It would be very useful for debugging.

 

Regards,

Alex

 

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