07-14-2019 11:16 PM
I generated an IP using HLS that have arrays both as input and output , I couldn't figure out how to utilize the generated ports and how to connect them in my block design with the zynq processor , a photo is attached for the generated IP with the ports .
I need help to know how and where to connect each of them and any example would be trurly helpful.
07-15-2019 04:24 AM
You would not normally use ap_memory with the Zynq processor.
The common ways of getting arrays into and out of a HLS block in Zynq are:
AXI-Lite - causes HLS to create an internal block RAM array, accessible over AXI from the Zynq (using the GP AXI Master ports). Getting data to and from this is relatively slow (AXI Lite only transfers a single data element at a time; it can't do burst transfers), but for something like configuration data (eg. a transformation matrix that will be applied to input images) it's perfect.
AXI Master - causes HLS to create an internal AXI Master which can connect to the Zynq's HP AXI Slave ports. This allows it to read/write data directly from/to the DDR memory attached to the PS. Performance can be very good, and the block can also perform random access (although you generally don't get both - for good performance you need to do reasonably large linear reads/writes). Perfect for things like large matrices or images that are being transformed, where you might want to read a row at a time, but you might not read the rows in order - and the data is far too large to easily store in block RAM.
AXI Stream - is a vastly simplified form of AXI that is essentially just data plus a few flow control lines. AXI Stream can only do linear reads (or writes) - you have to access every element exactly once, in the order they're provided. Normally they would be provided from an AXI DMA (or VDMA for images). The major advantage of AXI Streams is that if you have several blocks that all read from a stream and write to a stream, then you can chain them together. This reduces RAM bandwidth requirements, reduces resource usage, and reduces latency - all very good things.