10-26-2017 08:20 PM
I used hls co-simulation encountered problems, I have a huge array (4096×32×128bit )as input, the value read from the txt file.c-sim and synthesis are passed , but when co-simulation without any mistakes, only show some time out information.
Rtl simulation : 0 /1 [ 25027%] @"50000123000"
View the simulation waveform and there is no waveform.
Is there any solution to this problem?
10-26-2017 08:32 PM
It means that the module is locking up during cosimulation. Unfortunately debugging this can be extremely challenging. First step would be to remove any pragmas you've got and see if it'll work then - if it does then add them back in one at a time until it fails.
10-26-2017 08:47 PM
I'm your fans.I've read a lot of your answers. Thank you for your contribution to the community.
The key point is the huge array,the co-sim can be work well when the array is small(1x32x128bits).
I have try the other simple test project.Only push the input to the output(4096x32x128bits).It works well.It mean the tools can handle these huge array?
Thanks your reply.
10-26-2017 08:54 PM
How about 32x32x128-bit? I'm wondering whether it's just the 2-dimensional nature of the array that's causing problems for HLS.
I've worked with large arrays in the past and it's been OK. Of course, the most reliable way to check is to actually put the design on the FPGA and see what happens.