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Observer totemxm
Observer
791 Views
Registered: ‎08-24-2017

co-simulation problem

Hello everyone
I used hls co-simulation encountered problems, I have a huge array (4096×32×128bit )as input, the value read from the txt file.c-sim and synthesis are passed , but when co-simulation without any mistakes, only show some time out information.
Rtl simulation : 0 /1 [ 25027%] @"50000123000"
View the simulation waveform and there is no waveform.
Is there any solution to this problem?

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3 Replies
Scholar u4223374
Scholar
784 Views
Registered: ‎04-26-2015

Re: co-simulation problem

It means that the module is locking up during cosimulation. Unfortunately debugging this can be extremely challenging. First step would be to remove any pragmas you've got and see if it'll work then - if it does then add them back in one at a time until it fails.

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Observer totemxm
Observer
772 Views
Registered: ‎08-24-2017

Re: co-simulation problem

hi u4223374

I'm your fans.I've read a lot of your answers. Thank you for your contribution to the community.

The key point is the huge array,the co-sim can be work well when the array is small(1x32x128bits).

I have try the other simple test project.Only push the input to the output(4096x32x128bits).It works well.It mean the tools can handle these huge array?

Thanks your reply.

 

 

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Scholar u4223374
Scholar
769 Views
Registered: ‎04-26-2015

Re: co-simulation problem

How about 32x32x128-bit? I'm wondering whether it's just the 2-dimensional nature of the array that's causing problems for HLS.

 

I've worked with large arrays in the past and it's been OK. Of course, the most reliable way to check is to actually put the design on the FPGA and see what happens.

 

 

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