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Participant
Participant
949 Views
Registered: ‎10-03-2017

error: expected ')'

 

void pavilion_hw(T LabelS1[DIM1][DIM2], T out predict_label1[DIMa][DIMb], T precision1[DIMc][DIMd],T prob_estimates_t1[DIMe][DIMf])

error :
where labels1: input and predict_label1 T precision1,T prob_estimates_t1:output

 

 

src1/main.cpp:214:47: error: expected ')'
void pavilion_hw(T LabelS1[DIM1][DIM2], T out predict_label1[DIMa][DIMb], T precision1[DIMc][DIMd],T prob_estimates_t1[DIMe][DIMf])

 

 

 

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Advisor
Advisor
928 Views
Registered: ‎04-26-2015

T out predict_label1[DIMa][DIMb]

This is not a valid declaration. C does not have the port direction defined; HLS just infers that from the code. Delete the "out" and it should work.

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Xilinx Employee
Xilinx Employee
890 Views
Registered: ‎08-01-2008

Can you please provide detail . You can refer some example design here
https://github.com/Xilinx/HLx_Examples

you can also check this quick look video
https://www.xilinx.com/video/hardware/getting-started-vivado-high-level-synthesis.html
Thanks and Regards
Balkrishan
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