I am designing a core with Vivado HLS. In the core, I have a loop which reads data from an axi-stream and writes them to an m-axi interface. I want to have burst accesses, and the core works well when I make the axis interface register off. I mean:
#pragma HLS INTERFACE axis off port=stream_in
But if I add register to the axis interface (means removing off in the above pragma) , scheduling will fails to pipeline the design completely and there will be an extra latency for reading from the stream and then writing it. (each m-axi write takes two clock cycles)
This is OK and I understand the behavior. My problem is when I want to instantiate the above core in a hierarchy. If the above core gets input stream from an internal variable, the latency problem discussed above will happen. I want to know whether there's a way to carry input stream properties to the internal variables. I want to make the axis register off in the internal variable which is input to the above core.