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Adventurer
Adventurer
954 Views
Registered: ‎03-30-2017

mixed width BRAM

Does Vivado HLS supports mixed width dual port (different width ports A and B) BRAM synthesis?

If yes, then how?

If no, then I'd like to request that feature.

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Xilinx Employee
Xilinx Employee
939 Views
Registered: ‎05-22-2018

Hi @ifutritski ,

Please check page no.224 of below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/xst_v6s6.pdf

Hope the information will be helpful.

Thanks,

Raj

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Advisor
Advisor
910 Views
Registered: ‎04-26-2015

(1) No, not supported.

 

(2) How would you like it implemented? How would you describe something in C that would imply different port widths?

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Adventurer
Adventurer
902 Views
Registered: ‎03-30-2017

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Adventurer
Adventurer
899 Views
Registered: ‎03-30-2017

It can be described this way:

typedef union {
u8 wr_port[1024];
u32 rd_port[256];
} mixed_width_dpram_t;

 

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Advisor
Advisor
886 Views
Registered: ‎04-26-2015

Hmm, interesting idea. It's pretty tempting; now that you've posted the union idea I can see a bunch of places where this could make a lot of sense.

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Adventurer
Adventurer
871 Views
Registered: ‎03-30-2017

the question is how we make it an Enhancement request?

Hello, Xilinx!?

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Adventurer
Adventurer
812 Views
Registered: ‎03-30-2017

I am attaching a small design example for "mixed width BRAM" implementation.

  1. it syntheses as is, but doesn't infer a "mixed width BRAM" and as a result it uses 530 LUTs, 129 Muxes, 152 FFs and 1 BRAM. If a "mixed width BRAM" will be infered, expected resource utilization will be ~ 10 LUTs, ~10 FFs for ap_ctrl logic only

  2. The source code has #pragma HLS DATAFLOW commented out, because synthesis fails if uncommented - that's should be fixed!
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