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rlatlwnd00
Visitor
Visitor
1,911 Views
Registered: ‎12-26-2016

timing analysis AXI4 -stream using HLS sobelfilter

Hello, I'm S.J Kim

I analyze AXI4-STREAM for mapping the input data

but, OUT_STREAM_TVALID is not operation.

 

capture.JPG

 

 

I set to random clock (INPUT tvalid,tready,tuser,reset,clk, etc. )
but, OUTPUT_STREAM_TVALID is not operation.

can you tell me what is the problem?

i attached the source file.

thanks you.

 

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2 Replies
hpoetzl
Voyager
Voyager
1,865 Views
Registered: ‎06-24-2013

Hey @rlatlwnd00

 

The project you attached is missing the sobel_filter sources so it's hard to tell why this fails.

Also note that you are on a quite old version of Vivado (2014.4), so it might be a good idea to upgrade.

 

All the best,

Herbert

-------------- Yes, I do this for fun!
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florentw
Moderator
Moderator
912 Views
Registered: ‎11-09-2015

The issue is probably that the core needs to be reseted first


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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