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Observer syqhhseu
Observer
635 Views
Registered: ‎08-27-2012

ug871 chapter 11 lab1 can't run correct in vivado 2018.3/2019.1

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when I test ug871 chap.11 example, I find a few issue.

1. If select option ‘vivado synthesis’,hls generates error:

source run_vivadosyn.tcl -notrace
Cannot find packaged HLS IP
while executing
"error "Cannot find packaged HLS IP""
invoked from within
"if { ![file exists $ip_repo_path] } {
error "Cannot find packaged HLS IP"
}"
(file "run_vivadosyn.tcl" line 33)
INFO: [Common 17-206] Exiting Vivado at Sun Jun 2 19:34:35 2019...
ERROR: [HLS 200-478] vivado returned an error child process exited abnormally
command 'ap_source' returned error code
while executing
"source D:/hh/lab1/fir_prj/solution1/export.tcl"
invoked from within
"hls::main D:/hh/lab1/fir_prj/solution1/export.tcl"
("uplevel" body line 1)
invoked from within
"uplevel 1 hls::main {*}$args"
(procedure "hls_proc" line 5)
invoked from within
"hls_proc $argv"
Finished export RTL.

2.If unselect any option,vivado hls can generate sysgen IP that can't be correct used in system generator 2019.1(matlab 2019a).

input port 'input_val_V_dout' type is illegal.system generator Run errors:

Port is being driven by an incorrect type. "input_val_V_dout" expects to be driven by a signal of type illegal
Error occurred during "Rate and Type Error Checking".


Reported by:
'fir_sysgen/Vivado HLS'
A summary of Sysgen errors has been written to 'D:/hh/lab1/fir_sysgen_sysgen_error.log'

Reported by:
'fir_sysgen/Vivado HLS'
The S-function 'sysgen' in 'fir_sysgen/input_val_V_read' has specified the option SS_OPTION_PORT_SAMPLE_TIMES_ASSIGNED and specified inherited for sample time number 0. Inheriting a sample time is not supported when specifying SS_OPTION_PORT_SAMPLE_TIMES_ASSIGNED

IMG_20190602_205613.jpg
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1 Solution

Accepted Solutions
Moderator
Moderator
468 Views
Registered: ‎11-21-2018

Re: ug871 chapter 11 lab1 can't run correct in vivado 2018.3/2019.1

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Hi @syqhhseu 

 

I was able to reproduce your error, and I found the solution. 

The problem is because the ports output_val_V_din and input_val_V_dout are wrongly defined as type 'bool' in 2018.3/2019.1 versions. 

The correct values for these ports should be 'Signed' as shown below. 

UG871_Error.PNG

 

To correct the error, you can manually changed the value of the ports in the file auxiliary.xml located in fir_prj/solution1/impl/sysgen. I have attached the corrected file to the post as referance. 

After you have updated the port value, you can retry the tutorial starting from Step 2. 

 

I have flagged this issue internally, and it should be corrected in a later release. 

Regards, 

 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

5 Replies
Observer syqhhseu
Observer
589 Views
Registered: ‎08-27-2012

Re: ug871 chapter 11 lab1 can't run correct in vivado 2018.3/2019.1

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anybody can slove this problem, thank you.

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Moderator
Moderator
538 Views
Registered: ‎11-21-2018

Re: ug871 chapter 11 lab1 can't run correct in vivado 2018.3/2019.1

Jump to solution

Hi @syqhhseu 

 

Can I just check you are using the latest version of UG871

Which step exactly gives you the error? I can't seem to find a step which asks you to select option 'Vivado Synthesis'. 

 

For Step 1, were you using Windows or Linux? If you are using Windows, can you make sure the path length to the tutorial is as short as possible. Alternitively, could you use Linux and see if you get the same error (or use Windows if Linux gave you the error previously)? 

Regards, 

 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Observer syqhhseu
Observer
526 Views
Registered: ‎08-27-2012

Re: ug871 chapter 11 lab1 can't run correct in vivado 2018.3/2019.1

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thanks. According to UG871 guide, you will find error in step 2.

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Moderator
Moderator
469 Views
Registered: ‎11-21-2018

Re: ug871 chapter 11 lab1 can't run correct in vivado 2018.3/2019.1

Jump to solution

Hi @syqhhseu 

 

I was able to reproduce your error, and I found the solution. 

The problem is because the ports output_val_V_din and input_val_V_dout are wrongly defined as type 'bool' in 2018.3/2019.1 versions. 

The correct values for these ports should be 'Signed' as shown below. 

UG871_Error.PNG

 

To correct the error, you can manually changed the value of the ports in the file auxiliary.xml located in fir_prj/solution1/impl/sysgen. I have attached the corrected file to the post as referance. 

After you have updated the port value, you can retry the tutorial starting from Step 2. 

 

I have flagged this issue internally, and it should be corrected in a later release. 

Regards, 

 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

Moderator
Moderator
431 Views
Registered: ‎11-21-2018

Re: ug871 chapter 11 lab1 can't run correct in vivado 2018.3/2019.1

Jump to solution
Hi @syqhhseu,

Were you able to solve the issue by following the steps above? If so, could you make the answer as a solution? This will help other users find the solution faster.

If it did not solve the issue, please let me know.

Regards,
Aoife
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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