cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
7,899 Views
Registered: ‎12-04-2014

what are the timing relationship for every vivado hls interface component such as ap_vld, ap_fifo and so on?

vivado has many interface component such as ap_vld, ap_fifo and so on. I'am no sure what's the timing requirement for them. Is there any materials descripting my question ? chinese material the best .

0 Kudos
1 Reply
Highlighted
Xilinx Employee
Xilinx Employee
7,882 Views
Registered: ‎03-22-2011

Re: what are the timing relationship for every vivado hls interface component such as ap_vld, ap_fifo and so on?

In 2014.4 UG902 (Vivado HLS USer Guide), refer to pp 497-515 for timing diagrams.

Sorry, I'm not sure if there is a Chinese vesion of this document. 

0 Kudos