04-08-2021 02:12 AM
I have designed a circuit using vhdl language. When I synthesis that design using Vivado 2020.2 and xilinx ISE 14.7
both tools showing different utilization for the same FPGA boards.
My utilization for Artix 7 (xc7a100Tlcsg324) in Vivado 2020.2
Slice LUTS -- 179
Slice Registers -- 120
My utilization for Artix 7 (xc7a100Tlcsg324) in Xilinx ISE 14.7
Slice LUTS -- 291
Slice Registers -- 113
I don't why ?? Can anyone please help me to understand??
04-08-2021 09:43 AM - edited 04-08-2021 09:44 AM
Yes, this kind of result is expected.
ISE uses different routing algorithms compared to Vivado.
In Vivado, we can see more optimized placement & routing, hence optimized resource utilization.
Also, if the timing constraints are different for ISE & Vivado projects, the resources may vary as the tool tries to place & route the design so as to meet the timing constraint.
04-08-2021 11:20 AM
As @hpbhat says , its mainly down to them being two totally different tools.
A few key differences,
ISE works on assumption all clocks are independent unless you say, whilst Vivado is the opposite way around,
Thinking about that , I might have that the wrong way round, but some one will correct us.
Both tools have different algorithms, Vivado is meant to be 100 % deterministic, whilst ISE uses a form of artificial annealing , i.e. a bit of a randomness,
Both tools, work till they meet the timing constraints, and then stop.
So depending how ISE and Vivado start compiling your code, they might well come to a different first answer that meets your timing constraints.
Its also a truism, that in ISE days, people used to at most put a constraint on the clock frequencies in
whilst in Vivado, you need to constrain the clocks and any relationships between them, so the constraints are different,
Out of interest, I have a few designs, some are bigger in Vivado than ISE, some are smaller,
All meet constraints, so I do not worry,