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1,522 Views
Registered: ‎01-18-2018

32 bit inputs implementation error

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i'm trying to make a pwm module that i want to use later with the sdk 

the module has two 32 bit inputs, the first is pwm up time and the second is pwmperiod 

 

the simulation is good but when i tried to implement the design, i had an placing error ( number of unplaced terminals is greater ....)

as i understand vivado tries to give the two inputs a port with 64 bits

my purpose is to assign a value to them from the sdk 

i tried declaring them as wires, integers, reg     same error

 

module pwm(
    input clk,
    input enable,
    output pwm_out,
   input [31:0]  pwm_val,
    input [31:0] pwm_period
    );

thank you

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1 Solution

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2,072 Views
Registered: ‎01-18-2018

Re: 32 bit inputs implementation error

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I resolved the issue by editing the axi directly .

thank you

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5 Replies
Moderator
Moderator
1,491 Views
Registered: ‎01-16-2013

Re: 32 bit inputs implementation error

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@yassinema2018,

 

Can you please share the vivado.log or runme.log file present in <project>/<project>.runs/impl_1 folder?

 

Regards,
Syed

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1,481 Views
Registered: ‎01-18-2018

Re: 32 bit inputs implementation error

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hello thank you for your reply, here is the file :

 

 


*** Running vivado
with args -log pwm.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source pwm.tcl -notrace


****** Vivado v2017.4 (64-bit)
**** SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
**** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source pwm.tcl -notrace
Command: link_design -top pwm -part xc7z010clg400-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 25 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2017.4
INFO: [Device 21-403] Loading part xc7z010clg400-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [C:/Users/ysn/project_2/project_2.srcs/constrs_1/new/zybo.xdc]
Finished Parsing XDC File [C:/Users/ysn/project_2/project_2.srcs/constrs_1/new/zybo.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 534.137 ; gain = 307.266
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 545.832 ; gain = 11.695
INFO: [Timing 38-35] Done setting XDC timing constraints.

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 1b4535cae

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.295 . Memory (MB): peak = 1079.387 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 1b4535cae

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.320 . Memory (MB): peak = 1079.387 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: 179a90485

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.456 . Memory (MB): peak = 1079.387 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells

Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 179a90485

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.635 . Memory (MB): peak = 1079.387 ; gain = 0.000
INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells

Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 179a90485

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.687 . Memory (MB): peak = 1079.387 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Starting Connectivity Check Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1079.387 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 179a90485

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.707 . Memory (MB): peak = 1079.387 ; gain = 0.000

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 11a37f8d9

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.108 . Memory (MB): peak = 1079.387 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
22 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1079.387 ; gain = 545.250
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.286 . Memory (MB): peak = 1079.387 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'C:/Users/ysn/project_2/project_2.runs/impl_1/pwm_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file pwm_drc_opted.rpt -pb pwm_drc_opted.pb -rpx pwm_drc_opted.rpx
Command: report_drc -file pwm_drc_opted.rpt -pb pwm_drc_opted.pb -rpx pwm_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2017.4/data/ip'.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/ysn/project_2/project_2.runs/impl_1/pwm_drc_opted.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1079.387 ; gain = 0.000
INFO: [Chipscope 16-241] No debug cores found in the current design.
Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1079.387 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: f077b568

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.106 . Memory (MB): peak = 1079.387 ; gain = 0.000
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1079.387 ; gain = 0.000

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
ERROR: [Place 30-58] IO placement is infeasible. Number of unplaced terminals (64) is greater than number of available sites (50).
The following are banks with available pins:
IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: Out RangeId: 1 Drv: 12 has only 50 sites available on device, but needs 64 sites.
Term: pwm_period[0]
Term: pwm_period[1]
Term: pwm_period[2]
Term: pwm_period[3]
Term: pwm_period[4]
Term: pwm_period[5]
Term: pwm_period[6]
Term: pwm_period[7]
Term: pwm_period[8]
Term: pwm_period[9]
Term: pwm_period[10]
Term: pwm_period[11]
Term: pwm_period[12]
Term: pwm_period[13]
Term: pwm_period[14]
Term: pwm_period[15]
Term: pwm_period[16]
Term: pwm_period[17]
Term: pwm_period[18]
Term: pwm_period[19]
Term: pwm_period[20]
Term: pwm_period[21]
Term: pwm_period[22]
Term: pwm_period[23]
Term: pwm_period[24]
Term: pwm_period[25]
Term: pwm_period[26]
Term: pwm_period[27]
Term: pwm_period[28]
Term: pwm_period[29]
Term: pwm_period[30]
Term: pwm_period[31]
Term: pwm_val[0]
Term: pwm_val[1]
Term: pwm_val[2]
Term: pwm_val[3]
Term: pwm_val[4]
Term: pwm_val[5]
Term: pwm_val[6]
Term: pwm_val[7]
Term: pwm_val[8]
Term: pwm_val[9]
Term: pwm_val[10]
Term: pwm_val[11]
Term: pwm_val[12]
Term: pwm_val[13]
Term: pwm_val[14]
Term: pwm_val[15]
Term: pwm_val[16]
Term: pwm_val[17]
Term: pwm_val[18]
Term: pwm_val[19]
Term: pwm_val[20]
Term: pwm_val[21]
Term: pwm_val[22]
Term: pwm_val[23]
Term: pwm_val[24]
Term: pwm_val[25]
Term: pwm_val[26]
Term: pwm_val[27]
Term: pwm_val[28]
Term: pwm_val[29]
Term: pwm_val[30]
Term: pwm_val[31]


ERROR: [Place 30-58] IO placement is infeasible. Number of unplaced terminals (64) is greater than number of available sites (50).
The following are banks with available pins:
IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: Out RangeId: 1 Drv: 12 has only 50 sites available on device, but needs 64 sites.
Term: pwm_period[0]
Term: pwm_period[1]
Term: pwm_period[2]
Term: pwm_period[3]
Term: pwm_period[4]
Term: pwm_period[5]
Term: pwm_period[6]
Term: pwm_period[7]
Term: pwm_period[8]
Term: pwm_period[9]
Term: pwm_period[10]
Term: pwm_period[11]
Term: pwm_period[12]
Term: pwm_period[13]
Term: pwm_period[14]
Term: pwm_period[15]
Term: pwm_period[16]
Term: pwm_period[17]
Term: pwm_period[18]
Term: pwm_period[19]
Term: pwm_period[20]
Term: pwm_period[21]
Term: pwm_period[22]
Term: pwm_period[23]
Term: pwm_period[24]
Term: pwm_period[25]
Term: pwm_period[26]
Term: pwm_period[27]
Term: pwm_period[28]
Term: pwm_period[29]
Term: pwm_period[30]
Term: pwm_period[31]
Term: pwm_val[0]
Term: pwm_val[1]
Term: pwm_val[2]
Term: pwm_val[3]
Term: pwm_val[4]
Term: pwm_val[5]
Term: pwm_val[6]
Term: pwm_val[7]
Term: pwm_val[8]
Term: pwm_val[9]
Term: pwm_val[10]
Term: pwm_val[11]
Term: pwm_val[12]
Term: pwm_val[13]
Term: pwm_val[14]
Term: pwm_val[15]
Term: pwm_val[16]
Term: pwm_val[17]
Term: pwm_val[18]
Term: pwm_val[19]
Term: pwm_val[20]
Term: pwm_val[21]
Term: pwm_val[22]
Term: pwm_val[23]
Term: pwm_val[24]
Term: pwm_val[25]
Term: pwm_val[26]
Term: pwm_val[27]
Term: pwm_val[28]
Term: pwm_val[29]
Term: pwm_val[30]
Term: pwm_val[31]


ERROR: [Place 30-374] IO placer failed to find a solution
Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve.

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| IO Placement : Bank Stats |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| Id | Pins | Terms | Standards | IDelayCtrls | VREF | VCCO | VR | DCI |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| 0 | 0 | 0 | | | | | | |
| 13 | 0 | 0 | | | | | | |
| 34 | 50 | 0 | | | | | | |
| 35 | 50 | 3 | LVCMOS33(3) | | | +3.30 | YES | |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| | 100 | 3 | | | | | | |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+

IO Placement:
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| BankId | Terminal | Standard | Site | Pin | Attributes |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 35 | clk | LVCMOS33 | IOB_X0Y78 | L16 | |
| | enable | LVCMOS33 | IOB_X0Y61 | G15 | * |
| | pwm_out | LVCMOS33 | IOB_X0Y54 | M14 | |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+

WARNING: [Place 30-568] A LUT 'cnt2_i_2' is driving clock pin of 11 registers. This could lead to large hold time violations. First few involved registers are:
cnt0_reg[0] {FDRE}
cnt0_reg[1] {FDRE}
cnt0_reg[2] {FDRE}
cnt0_reg[3] {FDRE}
cnt0_reg[4] {FDRE}
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 14d6b6fc8

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1079.387 ; gain = 0.000
Phase 1 Placer Initialization | Checksum: 14d6b6fc8

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1079.387 ; gain = 0.000
ERROR: [Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
Ending Placer Task | Checksum: 14d6b6fc8

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1079.387 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
42 Infos, 1 Warnings, 0 Critical Warnings and 5 Errors encountered.
place_design failed
ERROR: [Common 17-69] Command failed: Placer could not place all instances
INFO: [Common 17-206] Exiting Vivado at Wed Jan 31 00:22:53 2018...

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Scholar markcurry
Scholar
1,461 Views
Registered: ‎09-16-2009

Re: 32 bit inputs implementation error

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@yassinema2018,

 

What FPGA / board are you targetting?

 

The tool is telling you that you're declaring module "pwm" as a top-level  FPGA, and trying to create an entire FPGA with that top-level.  I'm guessing you didn't assign a pinout, so the tool is making one up, but not finding sufficient pin sites for all those 64 PWM IO signals.

 

It's very likely you're NOT intending for the module "pwm" to be you're entire FPGA. Further, you probably have some goal in mind for how to get "pwm_val", and "pwm_period" down to your module.  Fill in some  more details here on exactly how you intend to use the pwm module.

 

Regards,

 

Mark

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1,449 Views
Registered: ‎01-18-2018

Re: 32 bit inputs implementation error

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thank you for replying

 

editing the axi lite requires declaring the module with its inputs and linking the inputs to the slave registers ( i'm I wrong ???), so before doing that i need to get my module to work, the problem is i need two 32 inputs to my module so i can control the pwm up time and the pwm period, but when i declare the two inputs vivado tries to assign a physical port to each of the 64 bits and that's the problem because i don't need hardware ports to be assigned to them i just want to assign them to the slave registers

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2,073 Views
Registered: ‎01-18-2018

Re: 32 bit inputs implementation error

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I resolved the issue by editing the axi directly .

thank you

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