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4,439 Views
Registered: ‎04-10-2018

Allow Combinatorial Loops

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Hi!

 

I have to implement a combinatorial loop (in a ring oscillator).

While implementing the design in vivado I get the error

 

"ERROR: [DRC LUTLP-1] Combinatorial Loop Alert: 733 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'. One net in the loop is INTERCON[732]. Please evaluate your design. The cells in the loop are: ... "

 

Therefor I added the suggested line to my xdc-file:

 

set_property ALLOW_COMBINATORIAL_LOOPS true [get_nets INTERCON[732]];

 

However, I still get the ERROR and it seems that vivado is simply ignoring the constraint.

 

Any ideas?

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Highlighted
5,208 Views
Registered: ‎04-10-2018

I've now tried a different thing, namely

 

attribute DONT_TOUCH : string;
attribute DONT_TOUCH of INTERCON : signal is "TRUE";
attribute ALLOW_COMBINATORIAL_LOOPS : string;
attribute ALLOW_COMBINATORIAL_LOOPS of INTERCON : signal is "TRUE";

 

and this actually seems to work (which I didn't expect to be honest).

I'll keep you posted!

View solution in original post

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Mentor
Mentor
4,408 Views
Registered: ‎02-24-2014

It's likely that the [get_nets  xxxx] is not actually finding the net as needed.  The way I would attack this is to attach the attribute to the net directly in the RTL, along with a DONT_TOUCH attribute.   Vivado synthesis will frequently "optimize" away or otherwise mangle combinatorial loops.    

 

Another tip for a ring oscillator..   They have a tendency to oscillate in unstable overtone modes unless you introduce some low pass filtering by using a majority gate with staggered (different taps on the delay line) inputs.    I've been thinking it's time to write and post a solid VHDL implementation for ring oscillators, because this subject comes up so frequently on the boards.

Don't forget to close a thread when possible by accepting a post as a solution.
Highlighted
4,401 Views
Registered: ‎04-10-2018

Thank you!

 

I'm not exactly sure, what you mean with "directly in the RTL".

You mean in my .vhdl file directly? Could you tell me the syntax for that?

I do have a DONT_TOUCH attribute in place already though.

 

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Mentor
Mentor
4,397 Views
Registered: ‎02-24-2014

Now that I think about it, I realize that I have to test this theory about putting the property in the RTL.  It might not work.

 

In the meantime,  here is how to get it working in Vivado.   It's been solved by @misdarvishi :

 

https://forums.xilinx.com/t5/Implementation/How-to-apply-set-property-ALLOW-COMBINATORIAL-LOOPS-TRUE-to-pass/td-p/779026

Don't forget to close a thread when possible by accepting a post as a solution.
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Highlighted
4,393 Views
Registered: ‎04-10-2018

Actually I've read that post already but didn't refer to it as helpfull as this code is placed in .xdc too, right?

I'll try that anyway.

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Highlighted
5,209 Views
Registered: ‎04-10-2018

I've now tried a different thing, namely

 

attribute DONT_TOUCH : string;
attribute DONT_TOUCH of INTERCON : signal is "TRUE";
attribute ALLOW_COMBINATORIAL_LOOPS : string;
attribute ALLOW_COMBINATORIAL_LOOPS of INTERCON : signal is "TRUE";

 

and this actually seems to work (which I didn't expect to be honest).

I'll keep you posted!

View solution in original post

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Mentor
Mentor
4,380 Views
Registered: ‎02-24-2014

@david.radakovits

 

you are officially awesome.     Kudos!

 

Now close the thread by accepting your post above as a solution.   Congratulations!

Don't forget to close a thread when possible by accepting a post as a solution.
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Teacher
Teacher
4,370 Views
Registered: ‎07-09-2009

ring oscilators, a very often covered topic

 

these are the two gods of xilinx, austin and ken,

 

https://forums.xilinx.com/t5/7-Series-FPGAs/How-to-implement-a-ring-oscillator-with-routings-of-FPGA-Where/td-p/768444

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Explorer
Explorer
4,061 Views
Registered: ‎05-08-2018

And...

 

Neither Ken, nor I are part of Xilinx.  Ken is retired and I am off to new challenges,

 

Austin Lesea

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