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Visitor nilnullzip
Registered: ‎09-19-2018

Are there issues with user implemented clock dividers?

I have a need for a custom clock divider. It takes a 2.5ns clock, and divides it down to generate arbitrary duty cycle and period clock down to 1.5MHz.

The divider logic is easy enough to implement in Verilog. The end result is a single register bit (so hazard free) that toggles as needed. I then instantiate a BUFG that buffers that signal and drives clock for the registers in the circuitry that occupies a large part of a VU9P. This clock does drive across all three SLRs. I attach a create_clock on the input of the BUFG to set timing constraints.

My question: is this OK? Or are there any issues that I should be aware of with creating my own clock generator like this? Is there anything else that I need to do to tell Vivado about this clock?

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Registered: ‎01-23-2009

Re: Are there issues with user implemented clock dividers?

First, this approach is not recommended. There are a couple of reasons why, but the main one is that you can get some bad hold time problems when bringing data from the base domain (in your case 2.5ns) to the divided domain.

In theory, if you really don't care about the phase of the divided clock with respect to the base clock, then this is "OK" (but still not highly recommended). However, if you do this, you must constrain it correctly - a create_clock on the output of the flip-flop is not the right way of doing it - you should do a create_generated_clock (where <my_ff> is the flip-flop that generates the clock and <divider> is the smallest possible divider)

create_generated_clock -name div_clk -source [get_pins <my_ff>/C] -divide_by <divider> [get_pins <my_ff>/Q]

Done this way, the tool will understand the relationship between the divided and undivided clock...

Alternate (more recommended) solutions are to use the base clock with a CE or use a BUFGCE - take a look at this post on either using the base clock and a CE generated by your "divider", or using a BUFGCE.

Note: In UltraScale/UltraScale+ if you use the BUFGCE solution, you need to put the net that is the output of the BUFG that is the base clock and the net that is the output of the BUFGCE that is the divided clock into the same CLOCK_GROUP (if you want to cross synchronously between the domains).