Showing results for 
Show  only  | Search instead for 
Did you mean: 
Registered: ‎05-15-2009

Automatic clock placement failed -- ISE 9.2-- Virtex4 xc4vlfx100 -- ERROR:Place:467

v4fx100,ise9.2 edk9.2

we use two ppcs,two MACs,318 brams, and 97% slice in our design.

but the clock placer failed.
ERROR:Place:467 - Automatic clock placement failed. Please attempt to analyze the Global clocking required for this design and either lock the clock placement or area locate the logic driven by the clocks so that the clocks may be placed in such a way that all logic driven by them may be routed. The main restriction on clock placement is that only 8 of 32 clocks sourced by Global buffers may enter a region. For further information see the "Global clocks" section in the Virtex-4 Hand-Book


I found the clk placer assign 9 clk in one clk region.

I have copyed the clk placement constraints found in the map log file to my ucf file and edited them according to my opinion. Then the clk placer and map successed,but the placer failed with 3 mac clk not routed.


How can I do next? any other suggestions other than adiusting clk placement constraints from map log?

Tags (2)
0 Kudos
0 Replies