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Visitor d.cardinale
Registered: ‎12-12-2013

Bidirectional SERDES, with different RX & TX clocks

I cannot get a simple bidirectional SERDES to place and route that is shown in UG381, Table 2-1. The first row, with DDR input using 2 BUFIOs and SDR output w/BUFPLL clock.


To troubleshoot, I reduced to one data bit and selected a larger part. If I substitute the OSERDES clock with the ISERDES clock PAR completes.


Otherwise, I get:


Place:1318 - User has over-constrained component io_inst/bufio2_buf0_inst.
   There are no placeable sites that satisfy the user constraints. Please review
   the user constraints on the driver component and the load components of


Can anyone confirm that this entry in Table 2-1 is indeed possible? If so, how?


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Community Manager
Community Manager
Registered: ‎07-23-2012

Re: Bidirectional SERDES, with different RX & TX clocks

Refer to http://www.xilinx.com/support/answers/41988.html
Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue.

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