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childrej
Visitor
Visitor
14,385 Views
Registered: ‎12-09-2009

Bit vectors and FPGA output pins

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Hi,

 

I have a 16-bit, bit vector which I have used for storing bits as fixed point binary and only need the first 8 significant bits output. Signals supply its value which are also 16 bits in length. I have tried setting the output port to a bit_vector and have said (15 downto 7) in the hope it will be equal to the most signifcant 8 bits of the signal.

 

It occured to me that I could just assign each of the 8 significant bits to an LED output pin on the board. Is it possible to specify which bit of a bit-vector goes to which port? And/Or is it advised to implement the output as 8 bits in the design first?

 

Thanks for looking

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hobson
Xilinx Employee
Xilinx Employee
19,168 Views
Registered: ‎04-15-2008

Hi childrej,

 

Hopefully I'm interpreting the root of your question correctly...

 

First off, you should probably be using the std_logic_1164 package in the IEEE library.  You can use std_logic and std_logic_vector instead of bit and bit_vector.

 

Anyway, you can use LOC constraints to call out each bit of an output (or input) bus and assign it to a pin.  So if you had:

 

my_output_bus : out std_logic_vector(7 downto 0);

...

signal my_internal_reg : std_logic_vector(15 downto 0);

...

my_output_bus <= my_internal_reg(15 downto 8);

...

 

 

Then you could put the following in your UCF file:

 

NET "my_output_bus(7)" LOC = AH23;

NET "my_output_bus(6)" LOC = K19;

NET "my_output_bus(5)" LOC = B46;

etc...

 

Such that AH23, K19, and B46 are valid pins in the pinout table for your device.  If those pins are connected to LEDs on your board, then you're good to go.

 

Regards,

-Hobson

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hobson
Xilinx Employee
Xilinx Employee
19,169 Views
Registered: ‎04-15-2008

Hi childrej,

 

Hopefully I'm interpreting the root of your question correctly...

 

First off, you should probably be using the std_logic_1164 package in the IEEE library.  You can use std_logic and std_logic_vector instead of bit and bit_vector.

 

Anyway, you can use LOC constraints to call out each bit of an output (or input) bus and assign it to a pin.  So if you had:

 

my_output_bus : out std_logic_vector(7 downto 0);

...

signal my_internal_reg : std_logic_vector(15 downto 0);

...

my_output_bus <= my_internal_reg(15 downto 8);

...

 

 

Then you could put the following in your UCF file:

 

NET "my_output_bus(7)" LOC = AH23;

NET "my_output_bus(6)" LOC = K19;

NET "my_output_bus(5)" LOC = B46;

etc...

 

Such that AH23, K19, and B46 are valid pins in the pinout table for your device.  If those pins are connected to LEDs on your board, then you're good to go.

 

Regards,

-Hobson

View solution in original post

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childrej
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14,361 Views
Registered: ‎12-09-2009

Hello,

 

My Apologees, I have been using std_logic_vector not bit_vector, not sure why i said that.

 

Anyway, thanks for your answer! :smileyvery-happy:

 

childrej 

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