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Visitor laomar
Visitor
329 Views
Registered: ‎05-12-2019

Bitstream generation not allowed for OOC modules

hello,

im trying to generate bitstream to get ebc file that allow me to identify the adress of LUT.

im using artix7 with vivado 2019 version.

in my code implementation and synthesis are correct.

but i cannot generate the bitstream , how can i do that without using io buffer because in my synthesis i have to use the option -mode out_of_context

 

thanks,

 

Capture.PNG

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11 Replies
Scholar drjohnsmith
Scholar
312 Views
Registered: ‎07-09-2009

Re: Bitstream generation not allowed for OOC modules

the error message is you can not create a bit stream for a OOC module
this is logical as bitstream has pins identified and a OOC module on its own is agnostic of pins,


what do you mean by address of LUT ?

can I ask what are you trying to do ?
make some IP that you can export ?

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Visitor laomar
Visitor
309 Views
Registered: ‎05-12-2019

Re: Bitstream generation not allowed for OOC modules

LUT(LOOK UP TABLE) im trying to identify the adress of lut in artix 7 so i need to generate the ebc file.
what kind of ip i can make?

you will find attached the vhdl code and the xdc file.

thanks

 

 

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Scholar drjohnsmith
Scholar
306 Views
Registered: ‎07-09-2009

Re: Bitstream generation not allowed for OOC modules

what do you mean by " trying to identify the address of lut"

Yes Look Up Table, but a LUT has no address .

in an OOC, the block is not even placed and routed, so the LUTs doesn't even have a location in the FPGA,

what do you mean by this address ?

 

BTW: Quick look at your code,

    can you try using tabs to format the code

    Im guessing your learning, dont use  ieee.std_logic_arith.all;

 

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Visitor laomar
Visitor
297 Views
Registered: ‎05-12-2019

Re: Bitstream generation not allowed for OOC modules

sorry but we have adresses for LUT in FPGA.

 

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Scholar drjohnsmith
Scholar
294 Views
Registered: ‎07-09-2009

Re: Bitstream generation not allowed for OOC modules

In that case, I'm very happy for you.

good luck.
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Scholar markcurry
Scholar
271 Views
Registered: ‎09-16-2009

Re: Bitstream generation not allowed for OOC modules

"Out Of Context" is a rather unfortunate name in that it really doesn't define well both what you as the designer are expecting, and what that tools are actually generating.

In all defintions, "OOC" means a partially implemented FPGA design.  Only parts of the full FPGA bit-stream generation process are done.

For me, "OOC" means stop after synthesis.  Meaning just generate a synthesized, and mapped netlist of the block in question, ready to be integrated into the rest of the design.

For others, "OOC" may mean doing placement, and perhaps routing of the block in question.  However, as I understand things, Xilinx is deprecating these OOC flows.

As far as I'm aware "OOC" never included actual bit-stream generation of a partial design.

As to your desire for the "address for LUT", are you looking for the Placement SITE of the LUT?

Regards,

Mark

Visitor laomar
Visitor
252 Views
Registered: ‎05-12-2019

Re: Bitstream generation not allowed for OOC modules

hello,

yes thats what im looking for exactly.

i divide all my design to many regions that i can identify each lut as you know in artix 7 we have 134600LUTS i succed to identify 133788luts.

i have problem when i use io pin that i can not place my dessign in the implementation. i tried severel time but no way.(you will find attached the previous error )

so when i used the option(-mode out_of_context) i succed to place my design but the problem was in bitstream generation.

 

thanks

 

Capture.PNGCapture1.PNG

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Scholar markcurry
Scholar
244 Views
Registered: ‎09-16-2009

Re: Bitstream generation not allowed for OOC modules

I'm not clear why you're using OOC in order to solve your placement problems.  The Placement problems seem to indicate you're trying to put too many logic cells inside the floorplanning region you've defined.  (3601 slices requested, 3600 slices available).  I'd focus on the original problem rather than the derived OOC problem.  Ditch the OOC flows - it's only confusing the picture.

Just curious - are you sure this level of detailed floorplanning is required?  The tools work much better with less floorplanning constraints applied.  Are you trying to reach some very high internal clock speeds?  (Like > 500 MHz?)

I've no knowledge regarding your specific design - yours may require such a flow. My experiences show that floorplanning is the rare exception (< 1% of my FPGAs) rather than the rule.

Regards,

Mark

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Visitor laomar
Visitor
221 Views
Registered: ‎05-12-2019

Re: Bitstream generation not allowed for OOC modules

i didn't understand i haven't a big experience with vivado.
so can u please explain to me what i have to add
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Scholar markcurry
Scholar
219 Views
Registered: ‎09-16-2009

Re: Bitstream generation not allowed for OOC modules

If you don't have a lot of experience with Vivado, then I strongly suggest REMOVING all pblock (floorplanning) constraints.  Just apply timing constraints (and top-level pin LOCs), and let the tool work at meeting timing.

Regards,

Mark

Xilinx Employee
Xilinx Employee
37 Views
Registered: ‎05-22-2018

Re: Bitstream generation not allowed for OOC modules

Hi @laomar ,

Please update on the issue? Is it resolved?

Do you have further queries on this? If not, can you please mark the response that resolved your issue, as Accepted Solution.

Thanks,

Raj

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