12-02-2019 10:01 AM
im trying to generate bitstream to get ebc file that allow me to identify the adress of LUT.
im using artix7 with vivado 2019 version.
in my code implementation and synthesis are correct.
but i cannot generate the bitstream , how can i do that without using io buffer because in my synthesis i have to use the option -mode out_of_context
12-02-2019 10:38 AM
12-02-2019 10:44 AM
12-02-2019 10:48 AM - edited 12-02-2019 10:50 AM
what do you mean by " trying to identify the address of lut"
Yes Look Up Table, but a LUT has no address .
in an OOC, the block is not even placed and routed, so the LUTs doesn't even have a location in the FPGA,
what do you mean by this address ?
BTW: Quick look at your code,
can you try using tabs to format the code
Im guessing your learning, dont use ieee.std_logic_arith.all;
12-02-2019 10:51 AM
12-02-2019 12:08 PM
"Out Of Context" is a rather unfortunate name in that it really doesn't define well both what you as the designer are expecting, and what that tools are actually generating.
In all defintions, "OOC" means a partially implemented FPGA design. Only parts of the full FPGA bit-stream generation process are done.
For me, "OOC" means stop after synthesis. Meaning just generate a synthesized, and mapped netlist of the block in question, ready to be integrated into the rest of the design.
For others, "OOC" may mean doing placement, and perhaps routing of the block in question. However, as I understand things, Xilinx is deprecating these OOC flows.
As far as I'm aware "OOC" never included actual bit-stream generation of a partial design.
As to your desire for the "address for LUT", are you looking for the Placement SITE of the LUT?
12-02-2019 12:47 PM - edited 12-02-2019 12:55 PM
yes thats what im looking for exactly.
i divide all my design to many regions that i can identify each lut as you know in artix 7 we have 134600LUTS i succed to identify 133788luts.
i have problem when i use io pin that i can not place my dessign in the implementation. i tried severel time but no way.(you will find attached the previous error )
so when i used the option(-mode out_of_context) i succed to place my design but the problem was in bitstream generation.
12-02-2019 01:01 PM
I'm not clear why you're using OOC in order to solve your placement problems. The Placement problems seem to indicate you're trying to put too many logic cells inside the floorplanning region you've defined. (3601 slices requested, 3600 slices available). I'd focus on the original problem rather than the derived OOC problem. Ditch the OOC flows - it's only confusing the picture.
Just curious - are you sure this level of detailed floorplanning is required? The tools work much better with less floorplanning constraints applied. Are you trying to reach some very high internal clock speeds? (Like > 500 MHz?)
I've no knowledge regarding your specific design - yours may require such a flow. My experiences show that floorplanning is the rare exception (< 1% of my FPGAs) rather than the rule.
12-02-2019 01:55 PM
12-02-2019 02:00 PM
If you don't have a lot of experience with Vivado, then I strongly suggest REMOVING all pblock (floorplanning) constraints. Just apply timing constraints (and top-level pin LOCs), and let the tool work at meeting timing.
12-08-2019 08:07 PM