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simon02
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Registered: ‎07-23-2019

Can i implement a module in advance to fix timing then implement the other part of the code ?

Hello,

The story is that I am trying to using tri_mode_ethernet_mac for Ethernet on a customized FPGA borad so with customized ports. I previously found one net "gmii_rx_er" had timimg violating and fix it by overwriting the contraint of IP core. See the detail here: 

https://forums.xilinx.com/t5/Implementation/IP-Timing-violated-on-the-customized-FPGA-board/m-p/999478#M25467

 

As I added other functions that are not related to Ethernet in the firmware, I found a weird case. Another net "gmii_rx_dv" had timing violation and "gmii_rx_er" is fine if i change back to the defaut IP constraint. 

Also I tried if the firmware only contains Ethernet part function and using Performance_ExtraTimingOpt as strategy for implementation, there is no timing violation! So clearly to me, vivado has the ability to implemente it without timing violation. But the other part of the code is influncing it. 

 

So i was wondering, could i implemente the tri_mode_ethernet_mac ip core in advance with the no timing violation version, then merge the other part to the firmware?

 

Is the DONT_TOUCH be the one I should use? 

 

Thanks!

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hongh
Moderator
Moderator
446 Views
Registered: ‎11-04-2010

In general flow, I don't think you can implement one module in advance.

For timing closure, you can refer to the flow in UG949.

You can also consider PR flow described in UG909 to implement one module independently.

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liubo_fpga
Explorer
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Registered: ‎04-28-2013

ways 1:
you can first route the critical path
route_design -pins [...] -delay
and then route all design.
ways 2:
you can get the cells location of the nets in good design and
use place cell to copy the cells bel and site location.
also you can get the nodes information in good design
get_property ROUTE [get_nets gmii_ir_er]
then copy the nodes list information in final implementation.
set_property FIXED_ROUTE {nodes list} [get_nets gmii_ir_er]
nonsense
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yashp
Moderator
Moderator
392 Views
Registered: ‎01-16-2013

Hi,

Also you can check floorplanning P-block to restrict the module in specified boundries. This will limit the scope of placement and routing variation as compared to non P-block use case.

Also if you have one design let's say D1 implemented and you are making small changes in that design or add some small functionality (~5% change) then you can try incremental implementation. In this your older design D1 will be baseline for implementing the new changes.

This above information is not exactly what you are looking for but ways to achieve similar results.

Note: I have read that you have override the constraints generated by IP to solve the timing violations. This is not correct way to solve the timing violations. Because this will only show good results at software but hardware might show the failure.

Thanks,
Yash

 

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