Can you route from an IBUFDS to a PLL(E) directly? (Virtex7)
I needed to multiply a refclk by two to meet the period assumptions of a reference design. Normally the pcs-pma take an IBUFDS and runs it to a BUFG (and also, in parallel, a QPLL but not relevant here).
Initially I tried: refclk => IBUFDS => PLL-E => BUFG.
This works fine through synthesis (and sim) without problem. However in implementation it tries to place the PLL-E in a location of the Virtex7 that is not routeable from the IBUFDS for the rocket I/O refclk. There's an error about being in a different clock region?
This is solvable via an extra BUFG: refclk => IBUFDS => BUFG => PLL-E => BUFG.
However is this the right solution? It seems wasteful of a BUFG element for resource count and power? Was the placer just being stupid and there are possible PLL-E location choices that are directly routeable, perhaps with a location constraint?