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bitjockey
Adventurer
Adventurer
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Registered: ‎03-21-2011

Can you route from an IBUFDS to a PLL(E) directly? (Virtex7)

I needed to multiply a refclk by two to meet the period assumptions of a reference design.  Normally the pcs-pma take an IBUFDS and runs it to a BUFG (and also, in parallel, a QPLL but not relevant here). 

Initially I tried: refclk => IBUFDS => PLL-E => BUFG.

This works fine through synthesis (and sim) without problem.  However in implementation it tries to place the PLL-E in a location of the Virtex7 that is not routeable from the IBUFDS for the rocket I/O refclk.  There's an error about being in a different clock region?

This is solvable via an extra BUFG: refclk => IBUFDS => BUFG => PLL-E => BUFG.

However is this the right solution?  It seems wasteful of a BUFG element for resource count and power?  Was the placer just being stupid and there are possible PLL-E location choices that are directly routeable, perhaps with a location constraint?

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hongh
Moderator
Moderator
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Registered: ‎11-04-2010

Please check whether there is a PLL in the same clock region of IBUFDS_GTE2. If not, a BUFG is needed to route the net from IBUFDS_GTE2 to PLL.

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