UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Participant kwiatlab
Participant
8,826 Views
Registered: ‎01-19-2012

Can you specifiy a subset of pins to assign to, and have the tools choose from those?

Jump to solution

Hello,

I have an FPGA evaluation board and have made an expansion board for an application that accesses 32 I/O pins, or 16 differential pairs. Currently I hardcode the locations into my .UCF for each pin, but I am realizing that the way in which I have chosen them may not be ideal. Looking through the constraints guide I cannot find a command for which I can specify a subset of pins, and then have the tools only consider them.

For example say I have four possible I/O pins, AB1, AB2, AB3, and AB4 and internally have four data pins D1, D2, D3, D4. How can I have the tools choose the best possible routing for these data pins, but only consider the four AB pins above?

0 Kudos
1 Solution

Accepted Solutions
Instructor
Instructor
12,909 Views
Registered: ‎08-14-2007

Re: Can you specifiy a subset of pins to assign to, and have the tools choose from those?

Jump to solution

First, I'll say that there is at least one way to do what you're asking, but it's not clear that you'll get any benefit from it.  Your assumption is that the tools are better than you are at selecting IO sites for your design, while I've rarely found that to be the case.  But if you want to try it:

 

Method 1)

 

LOC or PROHIBIT all the other pins of the chip.  LOC pins that are fixed in your board design.  PROHIBIT any other pins to prevent them from being chosen for top level signals that haven't already been LOCed.  You already know the LOC syntax.  Check the Constraints Guide for the PROHIBIT syntax.

 

Method 2)

 

Use LOCATE rather than LOC to map a module to a site group.  This is described in the constraints guide with the usual style of "example" that makes little sense unless you already grasp the concept.  i.e. the "examples" are more like a BNF definition of the syntax and would create errors if you pasted them into a design.  If you can figure out how to use this method, you'll get kudos for posting your UCF here.

-- Gabor
0 Kudos
6 Replies
Historian
Historian
8,818 Views
Registered: ‎02-25-2008

Re: Can you specifiy a subset of pins to assign to, and have the tools choose from those?

Jump to solution

You should ALWAYS lock down the pin assignments. Your PCB doesn't change, therefore neither can your pin assignments.

----------------------------Yes, I do this for a living.
0 Kudos
Participant kwiatlab
Participant
8,815 Views
Registered: ‎01-19-2012

Re: Can you specifiy a subset of pins to assign to, and have the tools choose from those?

Jump to solution

Ah let me clarify. My PCB also has 16 inputs, which come from an external board, so I am able to change the assignment of the inputs as I need to.

 

More specifically, I have a 16-channel 10 GHz demultiplexer evaluation board with 32-SMA outputs. These go to a PCB that I have made, which takes these 32-SMA outputs and routes them into the Samtec interface my FPGA evaluation board has. So, I have the freedom to change around the SMA cables out of the DMUX to suit my needs.

0 Kudos
Historian
Historian
8,808 Views
Registered: ‎02-25-2008

Re: Can you specifiy a subset of pins to assign to, and have the tools choose from those?

Jump to solution

@kwiatlab wrote:

Ah let me clarify. My PCB also has 16 inputs, which come from an external board, so I am able to change the assignment of the inputs as I need to.

 

More specifically, I have a 16-channel 10 GHz demultiplexer evaluation board with 32-SMA outputs. These go to a PCB that I have made, which takes these 32-SMA outputs and routes them into the Samtec interface my FPGA evaluation board has. So, I have the freedom to change around the SMA cables out of the DMUX to suit my needs.


Well, you need to know which input is used, right? And you can't change the assignment after configuration; indeed, you can't change it after place and route!

 

So again, ALWAYS lock down your pin assignments.

----------------------------Yes, I do this for a living.
0 Kudos
Instructor
Instructor
12,910 Views
Registered: ‎08-14-2007

Re: Can you specifiy a subset of pins to assign to, and have the tools choose from those?

Jump to solution

First, I'll say that there is at least one way to do what you're asking, but it's not clear that you'll get any benefit from it.  Your assumption is that the tools are better than you are at selecting IO sites for your design, while I've rarely found that to be the case.  But if you want to try it:

 

Method 1)

 

LOC or PROHIBIT all the other pins of the chip.  LOC pins that are fixed in your board design.  PROHIBIT any other pins to prevent them from being chosen for top level signals that haven't already been LOCed.  You already know the LOC syntax.  Check the Constraints Guide for the PROHIBIT syntax.

 

Method 2)

 

Use LOCATE rather than LOC to map a module to a site group.  This is described in the constraints guide with the usual style of "example" that makes little sense unless you already grasp the concept.  i.e. the "examples" are more like a BNF definition of the syntax and would create errors if you pasted them into a design.  If you can figure out how to use this method, you'll get kudos for posting your UCF here.

-- Gabor
0 Kudos
Xilinx Employee
Xilinx Employee
8,790 Views
Registered: ‎07-01-2008

Re: Can you specifiy a subset of pins to assign to, and have the tools choose from those?

Jump to solution

The UCF constraint syntax supports LOC constraints with a comma seperated list of values. I'm not certain it works with I/O pins but it very well might.

0 Kudos
Xilinx Employee
Xilinx Employee
8,788 Views
Registered: ‎07-01-2008

Re: Can you specifiy a subset of pins to assign to, and have the tools choose from those?

Jump to solution

LOCATE is a PCF constraint that's not normally used as an input source to map. It can be done but it complicates the flow. Make sure that the user constraint is outside the Schematic Start/Schematic End defined area or it will be overritten by map.

0 Kudos